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bh=NVMx9s0p6eS3mdR74Q8qaGNUdHlTjWWP5rB6sIuitXE=; b=rEeqbBMZUGZCh24oPyyOLf9cFr9sPVkoqYdQTFhX6+DZ9gSPoeMrESrz6h6EMYs0eq iKre40DheKmPQZW3zJMXpsU364DPAf73UNShyDagIK+lc8PKjlxt4ora7CiDs2xeVkJ7 vdX2eLXXY5XlNArWpAt1oVemAv+nRR9LfGouPZN0X9eV481MSRzca2ohI1XLVfLBaGWd EcYVwQjiaEB7gdfMOdb5xipeeuecVEF8j1OoQ7bcJWFg8ySa55hshxZRR2q6tgbryutj qlzdew/z1UjDDhQrvXrTS+9ufEqZZuZGmLBTXmVj8kBfx+smhvkpPTNG/MPbVxPZ813X KWWg== X-Gm-Message-State: AGRZ1gJg9FU7jjFS8kv8cqV4q0l7XRWtYLImERFlkFCB9bLSueWa2hgl rYefdqijyMkcoxKFtc/KYbz18Q== X-Google-Smtp-Source: AJdET5eaE6wWngOfToyeWHX5LFNPjYG0JB2ezHRD6TDE5muhGdzlgTrkzgcYIpx/cPs3onlNv2XJmA== X-Received: by 2002:a1c:3a8d:: with SMTP id h135-v6mr1119470wma.92.1542186040945; Wed, 14 Nov 2018 01:00:40 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1088:2b4c:4d39:8b22:d570:822a]) by smtp.gmail.com with ESMTPSA id n7-v6sm16951441wrt.60.2018.11.14.01.00.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Nov 2018 01:00:40 -0800 (PST) From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard , Benjamin Gaignard Subject: [PATCH v4 1/4] dt-bindings: hwlock: Document STM32 hwspinlock bindings Date: Wed, 14 Nov 2018 10:00:24 +0100 Message-Id: <20181114090027.7580-2-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181114090027.7580-1-benjamin.gaignard@linaro.org> References: <20181114090027.7580-1-benjamin.gaignard@linaro.org> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Benjamin Gaignard Add bindings for STM32 hardware spinlock device Signed-off-by: Benjamin Gaignard Signed-off-by: Benjamin Gaignard Reviewed-by: Rob Herring --- version 4: - add Linaro SoB version 3 : - fix clock name in properties description version 2 : - change clock name from hwspinlock to hsem to be align with hardware documentation .../bindings/hwlock/st,stm32-hwspinlock.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt new file mode 100644 index 000000000000..adf4f000ea3d --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt @@ -0,0 +1,23 @@ +STM32 Hardware Spinlock Device Binding +------------------------------------- + +Required properties : +- compatible : should be "st,stm32-hwspinlock". +- reg : the register address of hwspinlock. +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific + hwlock, so the number of cells should be <1> here. +- clock-names : Must contain "hsem". +- clocks : Must contain a phandle entry for the clock in clock-names, see the + common clock bindings. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example of hwlock provider: + hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hsem"; + };