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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id j37sm1556962wms.39.2021.08.19.08.12.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Aug 2021 08:12:06 -0700 (PDT) From: Alexandre Bailon To: ohad@wizery.com, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, robh+dt@kernel.org Cc: matthias.bgg@gmail.com, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, stephane.leprovost@mediatek.com, gpain@baylibre.com, khilman@baylibre.com, Alexandre Bailon Subject: [PATCH v3 4/4] ARM64: mt8183: Add support of APU to mt8183 Date: Thu, 19 Aug 2021 17:13:40 +0200 Message-Id: <20210819151340.741565-5-abailon@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210819151340.741565-1-abailon@baylibre.com> References: <20210819151340.741565-1-abailon@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org This adds the support of APU to mt8183. Signed-off-by: Alexandre Bailon --- .../boot/dts/mediatek/mt8183-pumpkin.dts | 48 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 40 ++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index ee912825cfc60..7fbed2b7bc6f8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -37,6 +37,42 @@ scp_mem_reserved: scp_mem_region@50000000 { reg = <0 0x50000000 0 0x2900000>; no-map; }; + + vdev0vring0: vdev0vring0 { + compatible = "shared-dma-pool"; + size = <0 0x00008000>; + no-map; + }; + + vdev0vring1: vdev0vring1 { + compatible = "shared-dma-pool"; + size = <0 0x00008000>; + no-map; + }; + + vdev0buffer: vdev0buffer { + compatible = "shared-dma-pool"; + size = <0 0x00100000>; + no-map; + }; + + vdev1vring0: vdev1vring0 { + compatible = "shared-dma-pool"; + size = <0 0x00008000>; + no-map; + }; + + vdev1vring1: vdev1vring1 { + compatible = "shared-dma-pool"; + size = <0 0x00008000>; + no-map; + }; + + vdev1buffer: vdev1buffer { + compatible = "shared-dma-pool"; + size = <0 0x00100000>; + no-map; + }; }; leds { @@ -381,3 +417,15 @@ &scp { &dsi0 { status = "disabled"; }; + +&apu0 { + memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>; + memory-region-names = "vdev0buffer", "vdev0vring0", "vdev0vring1"; + status = "okay"; +}; + +&apu1 { + memory-region = <&vdev1buffer>, <&vdev1vring0>, <&vdev1vring1>; + memory-region-names = "vdev0buffer", "vdev0vring0", "vdev0vring1"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index f90df6439c088..bf3f315ad3b2f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1447,12 +1447,52 @@ ipu_adl: syscon@19010000 { #clock-cells = <1>; }; + apu0: apu@0x19100000 { + compatible = "mediatek,mt8183-apu"; + reg = <0 0x19180000 0 0x14000>; + interrupts = ; + + iommus = <&iommu M4U_PORT_IMG_IPUO>, + <&iommu M4U_PORT_IMG_IPU3O>, + <&iommu M4U_PORT_IMG_IPUI>; + + clocks = <&ipu_core0 CLK_IPU_CORE0_AXI>, + <&ipu_core0 CLK_IPU_CORE0_IPU>, + <&ipu_core0 CLK_IPU_CORE0_JTAG>; + + clock-names = "axi", "ipu", "jtag"; + + power-domains = <&spm MT8183_POWER_DOMAIN_VPU_CORE0>; + + status = "disabled"; + }; + ipu_core0: syscon@19180000 { compatible = "mediatek,mt8183-ipu_core0", "syscon"; reg = <0 0x19180000 0 0x1000>; #clock-cells = <1>; }; + apu1: apu@19200000 { + compatible = "mediatek,mt8183-apu"; + reg = <0 0x19280000 0 0x14000>; + interrupts = ; + + iommus = <&iommu M4U_PORT_CAM_IPUO>, + <&iommu M4U_PORT_CAM_IPU2O>, + <&iommu M4U_PORT_CAM_IPU3O>; + + clocks = <&ipu_core0 CLK_IPU_CORE1_AXI>, + <&ipu_core0 CLK_IPU_CORE1_IPU>, + <&ipu_core0 CLK_IPU_CORE1_JTAG>; + + clock-names = "axi", "ipu", "jtag"; + + power-domains = <&spm MT8183_POWER_DOMAIN_VPU_CORE1>; + + status = "disabled"; + }; + ipu_core1: syscon@19280000 { compatible = "mediatek,mt8183-ipu_core1", "syscon"; reg = <0 0x19280000 0 0x1000>;