From patchwork Fri Sep 24 03:39:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 12513971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86701C43219 for ; Fri, 24 Sep 2021 03:39:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6FC8F61242 for ; Fri, 24 Sep 2021 03:39:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244054AbhIXDlR (ORCPT ); Thu, 23 Sep 2021 23:41:17 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:46994 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S244051AbhIXDlQ (ORCPT ); Thu, 23 Sep 2021 23:41:16 -0400 X-UUID: e96adb574e2942968a2aacd4160bd1a7-20210924 X-UUID: e96adb574e2942968a2aacd4160bd1a7-20210924 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 953275642; Fri, 24 Sep 2021 11:39:39 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 24 Sep 2021 11:39:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 24 Sep 2021 11:39:38 +0800 From: Tinghan Shen To: , , , , CC: , , , , , Tinghan Shen Subject: [PATCH v7 1/6] dt-bindings: remoteproc: mediatek: Add binding for mt8195 scp Date: Fri, 24 Sep 2021 11:39:30 +0800 Message-ID: <20210924033935.2127-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210924033935.2127-1-tinghan.shen@mediatek.com> References: <20210924033935.2127-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Add mt8195 compatible to binding document. The description of required properties are also modified to reflect the hardware change between mt8183 and mt8195. The mt8195 doesn't have to control the scp clock on kernel side. Signed-off-by: Tinghan Shen Acked-by: Rob Herring --- Documentation/devicetree/bindings/remoteproc/mtk,scp.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.txt b/Documentation/devicetree/bindings/remoteproc/mtk,scp.txt index 3f5f78764b60..d64466eefbe3 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.txt +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.txt @@ -5,13 +5,15 @@ This binding provides support for ARM Cortex M4 Co-processor found on some Mediatek SoCs. Required properties: -- compatible Should be "mediatek,mt8183-scp" +- compatible Should be one of: + "mediatek,mt8183-scp" + "mediatek,mt8195-scp" - reg Should contain the address ranges for memory regions: SRAM, CFG, and L1TCM. - reg-names Contains the corresponding names for the memory regions: "sram", "cfg", and "l1tcm". -- clocks Clock for co-processor (See: ../clock/clock-bindings.txt) -- clock-names Contains the corresponding name for the clock. This +- clocks Required by mt8183. Clock for co-processor (See: ../clock/clock-bindings.txt) +- clock-names Required by mt8183. Contains the corresponding name for the clock. This should be named "main". Subnodes