diff mbox series

[2/6] arm64: dts: xilinx: zynqmp: Add RPU subsystem device node

Message ID 20211122053856.1342859-3-tanmay.shah@xilinx.com (mailing list archive)
State Superseded
Headers show
Series Add Xilinx RPU subsystem support | expand

Commit Message

Tanmay Shah Nov. 22, 2021, 5:38 a.m. UTC 
RPU subsystem can be configured in cluster-mode or split mode.
Also each r5 core has separate power domains.

Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

--
2.25.1

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diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 28dccb891a53..f4fb98ccb1b5 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -654,6 +654,23 @@  qspi: spi@ff0f0000 {
                        power-domains = <&zynqmp_firmware PD_QSPI>;
                };

+               r5fss: r5fss@ff9a0000 {
+                       compatible = "xlnx,zynqmp-r5fss";
+                       xlnx,cluster-mode = <1>;
+
+                        reg = <0x0 0Xff9a0000 0x0 0x228>;
+
+                       r5f_core0: r5f-0 {
+                               compatible = "xlnx,zynqmp-r5f";
+                               power-domains = <&zynqmp_firmware PD_RPU_0>;
+                       };
+
+                       r5f_core1: r5f-1 {
+                               compatible = "xlnx,zynqmp-r5f";
+                               power-domains = <&zynqmp_firmware PD_RPU_1>;
+                       };
+               };
+
                psgtr: phy@fd400000 {
                        compatible = "xlnx,zynqmp-psgtr-v1.1";
                        status = "disabled";