[v6,1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings

Commit Message

Tanmay Shah May 31, 2022, 11:43 p.m. UTC

Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem
(cluster).

Signed-off-by: Tanmay Shah <[e-mail]>
---

Changes in v6:
  - Add maxItems to sram and memory-region property

Changes in v5:
- Add constraints of the possible values of xlnx,cluster-mode property
- fix description of power-domains property for r5 core
- Remove reg, address-cells and size-cells properties as it is not required
- Fix description of mboxes property
- Add description of each memory-region and remove old .txt binding link
  reference in the description

Changes in v4:
  - Add memory-region, mboxes and mbox-names properties in example

Changes in v3:
  - None


 .../bindings/remoteproc/xlnx,r5f-rproc.yaml   | 129 ++++++++++++++++++
 include/dt-bindings/power/xlnx-zynqmp-power.h |   6 +
 2 files changed, 135 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml

Comments

Krzysztof Kozlowski June 1, 2022, 12:22 p.m. UTC | #1

On 01/06/2022 01:43, Tanmay Shah wrote:
> Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
> Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem
> (cluster).
> 
> Signed-off-by: Tanmay Shah <[e-mail]>
> ---
> 
> Changes in v6:
>   - Add maxItems to sram and memory-region property
> 
> Changes in v5:
> - Add constraints of the possible values of xlnx,cluster-mode property
> - fix description of power-domains property for r5 core
> - Remove reg, address-cells and size-cells properties as it is not required
> - Fix description of mboxes property
> - Add description of each memory-region and remove old .txt binding link
>   reference in the description
> 
> Changes in v4:
>   - Add memory-region, mboxes and mbox-names properties in example
> 
> Changes in v3:
>   - None
> 
> 
>  .../bindings/remoteproc/xlnx,r5f-rproc.yaml   | 129 ++++++++++++++++++
>  include/dt-bindings/power/xlnx-zynqmp-power.h |   6 +
>  2 files changed, 135 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> new file mode 100644
> index 000000000000..cbff1c201a89
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx R5F processor subsystem
> +
> +maintainers:
> +  - Ben Levinsky <[e-mail]>
> +  - Tanmay Shah <[e-mail]>
> +
> +description: |
> +  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
> +  real-time processing based on the Cortex-R5F processor core from ARM.
> +  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
> +  floating-point unit that implements the Arm VFPv3 instruction set.
> +
> +properties:
> +  compatible:
> +    const: xlnx,zynqmp-r5fss
> +
> +  xlnx,cluster-mode:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2]
> +    description: |
> +      The RPU MPCore can operate in split mode(Dual-processor performance), Safety
> +      lock-step mode(Both RPU cores execute the same code in lock-step,
> +      clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while
> +      core 1 runs normally). The processor does not support dynamic configuration.
> +      Switching between modes is only permitted immediately after a processor reset.
> +      If set to  1 then lockstep mode and if 0 then split mode.
> +      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
> +
> +patternProperties:
> +  "^r5f-[a-f0-9]+$":
> +    type: object
> +    description: |
> +      The RPU is located in the Low Power Domain of the Processor Subsystem.
> +      Each processor includes separate L1 instruction and data caches and
> +      tightly coupled memories (TCM). System memory is cacheable, but the TCM
> +      memory space is non-cacheable.
> +
> +      Each RPU contains one 64KB memory and two 32KB memories that
> +      are accessed via the TCM A and B port interfaces, for a total of 128KB
> +      per processor. In lock-step mode, the processor has access to 256KB of
> +      TCM memory.
> +
> +    properties:
> +      compatible:
> +        const: xlnx,zynqmp-r5f
> +
> +      power-domains:
> +        description: RPU core PM domain specifier
> +        maxItems: 1
> +
> +      mboxes:
> +        minItems: 1
> +        items:
> +          - description: mailbox channel to send data to RPU
> +          - description: mailbox channel to receive data from RPU
> +
> +      mbox-names:
> +        minItems: 1
> +        items:
> +          - const: tx
> +          - const: rx
> +
> +      sram:
> +        $ref: /schemas/types.yaml#/definitions/phandle-array
> +        maxItems: 8

Without minItems, this means maxItems=minItems and previously you had
here "minItems:1", so is it really what you want?

Anyway rest looks good to me.

Reviewed-by: Krzysztof Kozlowski <[e-mail]>

Best regards,
Krzysztof

Tanmay Shah June 1, 2022, 4:06 p.m. UTC | #2

On 6/1/22 5:22 AM, Krzysztof Kozlowski <[e-mail]> wrote:
> On 01/06/2022 01:43, Tanmay Shah wrote:
> > Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
> > Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem
> > (cluster).
> >
> > Signed-off-by: Tanmay Shah <[e-mail]>
> > ---
> >
> > Changes in v6:
> >    - Add maxItems to sram and memory-region property
> >
> > Changes in v5:
> > - Add constraints of the possible values of xlnx,cluster-mode property
> > - fix description of power-domains property for r5 core
> > - Remove reg, address-cells and size-cells properties as it is not required
> > - Fix description of mboxes property
> > - Add description of each memory-region and remove old .txt binding link
> >    reference in the description
> >
> > Changes in v4:
> >    - Add memory-region, mboxes and mbox-names properties in example
> >
> > Changes in v3:
> >    - None
> >
> >
> >   .../bindings/remoteproc/xlnx,r5f-rproc.yaml   | 129 ++++++++++++++++++
> >   include/dt-bindings/power/xlnx-zynqmp-power.h |   6 +
> >   2 files changed, 135 insertions(+)
> >   create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> > new file mode 100644
> > index 000000000000..cbff1c201a89
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> > @@ -0,0 +1,129 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx R5F processor subsystem
> > +
> > +maintainers:
> > +  - Ben Levinsky <[e-mail]>
> > +  - Tanmay Shah <[e-mail]>
> > +
> > +description: |
> > +  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
> > +  real-time processing based on the Cortex-R5F processor core from ARM.
> > +  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
> > +  floating-point unit that implements the Arm VFPv3 instruction set.
> > +
> > +properties:
> > +  compatible:
> > +    const: xlnx,zynqmp-r5fss
> > +
> > +  xlnx,cluster-mode:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [0, 1, 2]
> > +    description: |
> > +      The RPU MPCore can operate in split mode(Dual-processor performance), Safety
> > +      lock-step mode(Both RPU cores execute the same code in lock-step,
> > +      clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while
> > +      core 1 runs normally). The processor does not support dynamic configuration.
> > +      Switching between modes is only permitted immediately after a processor reset.
> > +      If set to  1 then lockstep mode and if 0 then split mode.
> > +      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
> > +
> > +patternProperties:
> > +  "^r5f-[a-f0-9]+$":
> > +    type: object
> > +    description: |
> > +      The RPU is located in the Low Power Domain of the Processor Subsystem.
> > +      Each processor includes separate L1 instruction and data caches and
> > +      tightly coupled memories (TCM). System memory is cacheable, but the TCM
> > +      memory space is non-cacheable.
> > +
> > +      Each RPU contains one 64KB memory and two 32KB memories that
> > +      are accessed via the TCM A and B port interfaces, for a total of 128KB
> > +      per processor. In lock-step mode, the processor has access to 256KB of
> > +      TCM memory.
> > +
> > +    properties:
> > +      compatible:
> > +        const: xlnx,zynqmp-r5f
> > +
> > +      power-domains:
> > +        description: RPU core PM domain specifier
> > +        maxItems: 1
> > +
> > +      mboxes:
> > +        minItems: 1
> > +        items:
> > +          - description: mailbox channel to send data to RPU
> > +          - description: mailbox channel to receive data from RPU
> > +
> > +      mbox-names:
> > +        minItems: 1
> > +        items:
> > +          - const: tx
> > +          - const: rx
> > +
> > +      sram:
> > +        $ref: /schemas/types.yaml#/definitions/phandle-array
> > +        maxItems: 8
> 
> Without minItems, this means maxItems=minItems and previously you had
> here "minItems:1", so is it really what you want?
> 

Ok. I misunderstood previous comment here in that case. I thought minIterms will be
1 by default. But, it is not that way. I will fix this in next revision.        

Thanks.

> Anyway rest looks good to me.
> 
> Reviewed-by: Krzysztof Kozlowski <[e-mail]>
> 
> Best regards,
> Krzysztof
>

Rob Herring (Arm) June 1, 2022, 6:42 p.m. UTC | #3

On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote:
> Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
> Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem
> (cluster).
> 
> Signed-off-by: Tanmay Shah <[e-mail]>
> ---
> 
> Changes in v6:
>   - Add maxItems to sram and memory-region property
> 
> Changes in v5:
> - Add constraints of the possible values of xlnx,cluster-mode property
> - fix description of power-domains property for r5 core
> - Remove reg, address-cells and size-cells properties as it is not required
> - Fix description of mboxes property
> - Add description of each memory-region and remove old .txt binding link
>   reference in the description
> 
> Changes in v4:
>   - Add memory-region, mboxes and mbox-names properties in example
> 
> Changes in v3:
>   - None
> 
> 
>  .../bindings/remoteproc/xlnx,r5f-rproc.yaml   | 129 ++++++++++++++++++
>  include/dt-bindings/power/xlnx-zynqmp-power.h |   6 +
>  2 files changed, 135 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> new file mode 100644
> index 000000000000..cbff1c201a89
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx R5F processor subsystem
> +
> +maintainers:
> +  - Ben Levinsky <[e-mail]>
> +  - Tanmay Shah <[e-mail]>
> +
> +description: |
> +  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
> +  real-time processing based on the Cortex-R5F processor core from ARM.
> +  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
> +  floating-point unit that implements the Arm VFPv3 instruction set.
> +
> +properties:
> +  compatible:
> +    const: xlnx,zynqmp-r5fss
> +
> +  xlnx,cluster-mode:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2]
> +    description: |
> +      The RPU MPCore can operate in split mode(Dual-processor performance), Safety
> +      lock-step mode(Both RPU cores execute the same code in lock-step,
> +      clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while
> +      core 1 runs normally). The processor does not support dynamic configuration.
> +      Switching between modes is only permitted immediately after a processor reset.
> +      If set to  1 then lockstep mode and if 0 then split mode.
> +      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
> +
> +patternProperties:
> +  "^r5f-[a-f0-9]+$":
> +    type: object
> +    description: |
> +      The RPU is located in the Low Power Domain of the Processor Subsystem.
> +      Each processor includes separate L1 instruction and data caches and
> +      tightly coupled memories (TCM). System memory is cacheable, but the TCM
> +      memory space is non-cacheable.
> +
> +      Each RPU contains one 64KB memory and two 32KB memories that
> +      are accessed via the TCM A and B port interfaces, for a total of 128KB
> +      per processor. In lock-step mode, the processor has access to 256KB of
> +      TCM memory.
> +
> +    properties:
> +      compatible:
> +        const: xlnx,zynqmp-r5f
> +
> +      power-domains:
> +        description: RPU core PM domain specifier
> +        maxItems: 1
> +
> +      mboxes:
> +        minItems: 1
> +        items:
> +          - description: mailbox channel to send data to RPU
> +          - description: mailbox channel to receive data from RPU
> +
> +      mbox-names:
> +        minItems: 1
> +        items:
> +          - const: tx
> +          - const: rx
> +
> +      sram:
> +        $ref: /schemas/types.yaml#/definitions/phandle-array
> +        maxItems: 8

minItems: 1
maxItems: 8
items:
  maxItems: 1

> +        description: |
> +          phandles to one or more reserved on-chip SRAM regions. Other than TCM,
> +          the RPU can execute instructions and access data from, the OCM memory,
> +          the main DDR memory, and other system memories.
> +
> +          The regions should be defined as child nodes of the respective SRAM
> +          node, and should be defined as per the generic bindings in,
> +          Documentation/devicetree/bindings/sram/sram.yaml
> +
> +      memory-region:
> +        description: |
> +          List of phandles to the reserved memory regions associated with the
> +          remoteproc device. This is variable and describes the memories shared with
> +          the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
> +          vrings, ...). This reserved memory region will be allocated on DDR memory.
> +        minItems: 1
> +        maxItems: 8
> +        items:
> +          - description: region used for RPU firmware image section
> +          - description: vdev buffer
> +          - description: vring0
> +          - description: vring1
> +        additionalItems: true
> +
> +    required:
> +      - compatible
> +      - power-domains
> +
> +    unevaluatedProperties: false
> +
> +required:
> +  - compatible
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    r5fss: r5fss {
> +        compatible = "xlnx,zynqmp-r5fss";
> +        xlnx,cluster-mode = <1>;
> +
> +        r5f-0 {
> +            compatible = "xlnx,zynqmp-r5f";
> +            power-domains = <&zynqmp_firmware 0x7>;
> +            memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
> +            mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
> +            mbox-names = "tx", "rx";
> +        };
> +
> +        r5f-1 {
> +            compatible = "xlnx,zynqmp-r5f";
> +            power-domains = <&zynqmp_firmware 0x8>;
> +            memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
> +            mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
> +            mbox-names = "tx", "rx";
> +        };
> +    };
> +...
> diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
> index 0d9a412fd5e0..618024cbb20d 100644
> --- a/include/dt-bindings/power/xlnx-zynqmp-power.h
> +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
> @@ -6,6 +6,12 @@
>  #ifndef _DT_BINDINGS_ZYNQMP_POWER_H
>  #define _DT_BINDINGS_ZYNQMP_POWER_H
>  
> +#define		PD_RPU_0	7
> +#define		PD_RPU_1	8
> +#define		PD_R5_0_ATCM	15
> +#define		PD_R5_0_BTCM	16
> +#define		PD_R5_1_ATCM	17
> +#define		PD_R5_1_BTCM	18
>  #define		PD_USB_0	22
>  #define		PD_USB_1	23
>  #define		PD_TTC_0	24
> -- 
> 2.25.1
> 
>

Tanmay Shah June 1, 2022, 7:05 p.m. UTC | #4

Hi Rob,

Thanks for reviews. Please find my comments below:

On 6/1/22 11:42 AM, Rob Herring wrote:
> On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote:
>> Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
>> Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem
>> (cluster).
>>
>> Signed-off-by: Tanmay Shah <[e-mail]>
>> ---
>>
>> Changes in v6:
>>    - Add maxItems to sram and memory-region property
>>
>> Changes in v5:
>> - Add constraints of the possible values of xlnx,cluster-mode property
>> - fix description of power-domains property for r5 core
>> - Remove reg, address-cells and size-cells properties as it is not required
>> - Fix description of mboxes property
>> - Add description of each memory-region and remove old .txt binding link
>>    reference in the description
>>
>> Changes in v4:
>>    - Add memory-region, mboxes and mbox-names properties in example
>>
>> Changes in v3:
>>    - None
>>
>>
>>   .../bindings/remoteproc/xlnx,r5f-rproc.yaml   | 129 ++++++++++++++++++
>>   include/dt-bindings/power/xlnx-zynqmp-power.h |   6 +
>>   2 files changed, 135 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
>> new file mode 100644
>> index 000000000000..cbff1c201a89
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
>> @@ -0,0 +1,129 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Xilinx R5F processor subsystem
>> +
>> +maintainers:
>> +  - Ben Levinsky <[e-mail]>
>> +  - Tanmay Shah <[e-mail]>
>> +
>> +description: |
>> +  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
>> +  real-time processing based on the Cortex-R5F processor core from ARM.
>> +  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
>> +  floating-point unit that implements the Arm VFPv3 instruction set.
>> +
>> +properties:
>> +  compatible:
>> +    const: xlnx,zynqmp-r5fss
>> +
>> +  xlnx,cluster-mode:
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    enum: [0, 1, 2]
>> +    description: |
>> +      The RPU MPCore can operate in split mode(Dual-processor performance), Safety
>> +      lock-step mode(Both RPU cores execute the same code in lock-step,
>> +      clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while
>> +      core 1 runs normally). The processor does not support dynamic configuration.
>> +      Switching between modes is only permitted immediately after a processor reset.
>> +      If set to  1 then lockstep mode and if 0 then split mode.
>> +      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
>> +
>> +patternProperties:
>> +  "^r5f-[a-f0-9]+$":
>> +    type: object
>> +    description: |
>> +      The RPU is located in the Low Power Domain of the Processor Subsystem.
>> +      Each processor includes separate L1 instruction and data caches and
>> +      tightly coupled memories (TCM). System memory is cacheable, but the TCM
>> +      memory space is non-cacheable.
>> +
>> +      Each RPU contains one 64KB memory and two 32KB memories that
>> +      are accessed via the TCM A and B port interfaces, for a total of 128KB
>> +      per processor. In lock-step mode, the processor has access to 256KB of
>> +      TCM memory.
>> +
>> +    properties:
>> +      compatible:
>> +        const: xlnx,zynqmp-r5f
>> +
>> +      power-domains:
>> +        description: RPU core PM domain specifier
>> +        maxItems: 1
>> +
>> +      mboxes:
>> +        minItems: 1
>> +        items:
>> +          - description: mailbox channel to send data to RPU
>> +          - description: mailbox channel to receive data from RPU
>> +
>> +      mbox-names:
>> +        minItems: 1
>> +        items:
>> +          - const: tx
>> +          - const: rx
>> +
>> +      sram:
>> +        $ref: /schemas/types.yaml#/definitions/phandle-array
>> +        maxItems: 8
> minItems: 1
> maxItems: 8
> items:
>    maxItems: 1

I have posted v7 which adds "minItems: 1".

However, I didn't get items: part. Is it required to have items: now?

Can I add items: part once TCM bindings are posted?

I understand that minItems and maxItems under sram property decides how 
many phandles sram can have.

However, maxItems: 1 under items: field what it describes?

Thanks.

>
>> +        description: |
>> +          phandles to one or more reserved on-chip SRAM regions. Other than TCM,
>> +          the RPU can execute instructions and access data from, the OCM memory,
>> +          the main DDR memory, and other system memories.
>> +
>> +          The regions should be defined as child nodes of the respective SRAM
>> +          node, and should be defined as per the generic bindings in,
>> +          Documentation/devicetree/bindings/sram/sram.yaml
>> +
>> +      memory-region:
>> +        description: |
>> +          List of phandles to the reserved memory regions associated with the
>> +          remoteproc device. This is variable and describes the memories shared with
>> +          the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
>> +          vrings, ...). This reserved memory region will be allocated on DDR memory.
>> +        minItems: 1
>> +        maxItems: 8
>> +        items:
>> +          - description: region used for RPU firmware image section
>> +          - description: vdev buffer
>> +          - description: vring0
>> +          - description: vring1
>> +        additionalItems: true
>> +
>> +    required:
>> +      - compatible
>> +      - power-domains
>> +
>> +    unevaluatedProperties: false
>> +
>> +required:
>> +  - compatible
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    r5fss: r5fss {
>> +        compatible = "xlnx,zynqmp-r5fss";
>> +        xlnx,cluster-mode = <1>;
>> +
>> +        r5f-0 {
>> +            compatible = "xlnx,zynqmp-r5f";
>> +            power-domains = <&zynqmp_firmware 0x7>;
>> +            memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
>> +            mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
>> +            mbox-names = "tx", "rx";
>> +        };
>> +
>> +        r5f-1 {
>> +            compatible = "xlnx,zynqmp-r5f";
>> +            power-domains = <&zynqmp_firmware 0x8>;
>> +            memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
>> +            mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
>> +            mbox-names = "tx", "rx";
>> +        };
>> +    };
>> +...
>> diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
>> index 0d9a412fd5e0..618024cbb20d 100644
>> --- a/include/dt-bindings/power/xlnx-zynqmp-power.h
>> +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
>> @@ -6,6 +6,12 @@
>>   #ifndef _DT_BINDINGS_ZYNQMP_POWER_H
>>   #define _DT_BINDINGS_ZYNQMP_POWER_H
>>   
>> +#define		PD_RPU_0	7
>> +#define		PD_RPU_1	8
>> +#define		PD_R5_0_ATCM	15
>> +#define		PD_R5_0_BTCM	16
>> +#define		PD_R5_1_ATCM	17
>> +#define		PD_R5_1_BTCM	18
>>   #define		PD_USB_0	22
>>   #define		PD_USB_1	23
>>   #define		PD_TTC_0	24
>> -- 
>> 2.25.1
>>
>>

Rob Herring (Arm) June 2, 2022, 3:14 p.m. UTC | #5

On Wed, Jun 01, 2022 at 12:05:09PM -0700, Tanmay Shah wrote:
> Hi Rob,
> 
> Thanks for reviews. Please find my comments below:
> 
> On 6/1/22 11:42 AM, Rob Herring wrote:
> > On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote:
> > > Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
> > > Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem
> > > (cluster).
> > > 
> > > Signed-off-by: Tanmay Shah <[e-mail]>
> > > ---
> > > 
> > > Changes in v6:
> > >    - Add maxItems to sram and memory-region property
> > > 
> > > Changes in v5:
> > > - Add constraints of the possible values of xlnx,cluster-mode property
> > > - fix description of power-domains property for r5 core
> > > - Remove reg, address-cells and size-cells properties as it is not required
> > > - Fix description of mboxes property
> > > - Add description of each memory-region and remove old .txt binding link
> > >    reference in the description
> > > 
> > > Changes in v4:
> > >    - Add memory-region, mboxes and mbox-names properties in example
> > > 
> > > Changes in v3:
> > >    - None
> > > 
> > > 
> > >   .../bindings/remoteproc/xlnx,r5f-rproc.yaml   | 129 ++++++++++++++++++
> > >   include/dt-bindings/power/xlnx-zynqmp-power.h |   6 +
> > >   2 files changed, 135 insertions(+)
> > >   create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> > > 
> > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> > > new file mode 100644
> > > index 000000000000..cbff1c201a89
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
> > > @@ -0,0 +1,129 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Xilinx R5F processor subsystem
> > > +
> > > +maintainers:
> > > +  - Ben Levinsky <[e-mail]>
> > > +  - Tanmay Shah <[e-mail]>
> > > +
> > > +description: |
> > > +  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
> > > +  real-time processing based on the Cortex-R5F processor core from ARM.
> > > +  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
> > > +  floating-point unit that implements the Arm VFPv3 instruction set.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: xlnx,zynqmp-r5fss
> > > +
> > > +  xlnx,cluster-mode:
> > > +    $ref: /schemas/types.yaml#/definitions/uint32
> > > +    enum: [0, 1, 2]
> > > +    description: |
> > > +      The RPU MPCore can operate in split mode(Dual-processor performance), Safety
> > > +      lock-step mode(Both RPU cores execute the same code in lock-step,
> > > +      clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while
> > > +      core 1 runs normally). The processor does not support dynamic configuration.
> > > +      Switching between modes is only permitted immediately after a processor reset.
> > > +      If set to  1 then lockstep mode and if 0 then split mode.
> > > +      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
> > > +
> > > +patternProperties:
> > > +  "^r5f-[a-f0-9]+$":
> > > +    type: object
> > > +    description: |
> > > +      The RPU is located in the Low Power Domain of the Processor Subsystem.
> > > +      Each processor includes separate L1 instruction and data caches and
> > > +      tightly coupled memories (TCM). System memory is cacheable, but the TCM
> > > +      memory space is non-cacheable.
> > > +
> > > +      Each RPU contains one 64KB memory and two 32KB memories that
> > > +      are accessed via the TCM A and B port interfaces, for a total of 128KB
> > > +      per processor. In lock-step mode, the processor has access to 256KB of
> > > +      TCM memory.
> > > +
> > > +    properties:
> > > +      compatible:
> > > +        const: xlnx,zynqmp-r5f
> > > +
> > > +      power-domains:
> > > +        description: RPU core PM domain specifier
> > > +        maxItems: 1
> > > +
> > > +      mboxes:
> > > +        minItems: 1
> > > +        items:
> > > +          - description: mailbox channel to send data to RPU
> > > +          - description: mailbox channel to receive data from RPU
> > > +
> > > +      mbox-names:
> > > +        minItems: 1
> > > +        items:
> > > +          - const: tx
> > > +          - const: rx
> > > +
> > > +      sram:
> > > +        $ref: /schemas/types.yaml#/definitions/phandle-array
> > > +        maxItems: 8
> > minItems: 1
> > maxItems: 8
> > items:
> >    maxItems: 1
> 
> I have posted v7 which adds "minItems: 1".
> 
> However, I didn't get items: part. Is it required to have items: now?

Yes.
> 
> Can I add items: part once TCM bindings are posted?

No.

> I understand that minItems and maxItems under sram property decides how many
> phandles sram can have.
> 
> However, maxItems: 1 under items: field what it describes?

'phandle-array' is really a matrix type because we can have phandles 
plus argument cells. So you have to define each of the 1-8 entries is a 
single phandle cell (and no arg cells).

Rob

Tanmay Shah June 2, 2022, 4:08 p.m. UTC | #6

On 6/2/22 8:14 AM, Rob Herring wrote:
> On Wed, Jun 01, 2022 at 12:05:09PM -0700, Tanmay Shah wrote:
>> Hi Rob,
>>
>> Thanks for reviews. Please find my comments below:
>>
>> On 6/1/22 11:42 AM, Rob Herring wrote:
>>> On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote:
>>>> Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing
>>>> Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem
>>>> (cluster).
>>>>
>>>> Signed-off-by: Tanmay Shah <[e-mail]>
>>>> ---
>>>>
>>>> Changes in v6:
>>>>     - Add maxItems to sram and memory-region property
>>>>
>>>> Changes in v5:
>>>> - Add constraints of the possible values of xlnx,cluster-mode property
>>>> - fix description of power-domains property for r5 core
>>>> - Remove reg, address-cells and size-cells properties as it is not required
>>>> - Fix description of mboxes property
>>>> - Add description of each memory-region and remove old .txt binding link
>>>>     reference in the description
>>>>
>>>> Changes in v4:
>>>>     - Add memory-region, mboxes and mbox-names properties in example
>>>>
>>>> Changes in v3:
>>>>     - None
>>>>
>>>>
>>>>    .../bindings/remoteproc/xlnx,r5f-rproc.yaml   | 129 ++++++++++++++++++
>>>>    include/dt-bindings/power/xlnx-zynqmp-power.h |   6 +
>>>>    2 files changed, 135 insertions(+)
>>>>    create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
>>>> new file mode 100644
>>>> index 000000000000..cbff1c201a89
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
>>>> @@ -0,0 +1,129 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Xilinx R5F processor subsystem
>>>> +
>>>> +maintainers:
>>>> +  - Ben Levinsky <[e-mail]>
>>>> +  - Tanmay Shah <[e-mail]>
>>>> +
>>>> +description: |
>>>> +  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
>>>> +  real-time processing based on the Cortex-R5F processor core from ARM.
>>>> +  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
>>>> +  floating-point unit that implements the Arm VFPv3 instruction set.
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    const: xlnx,zynqmp-r5fss
>>>> +
>>>> +  xlnx,cluster-mode:
>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>> +    enum: [0, 1, 2]
>>>> +    description: |
>>>> +      The RPU MPCore can operate in split mode(Dual-processor performance), Safety
>>>> +      lock-step mode(Both RPU cores execute the same code in lock-step,
>>>> +      clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while
>>>> +      core 1 runs normally). The processor does not support dynamic configuration.
>>>> +      Switching between modes is only permitted immediately after a processor reset.
>>>> +      If set to  1 then lockstep mode and if 0 then split mode.
>>>> +      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
>>>> +
>>>> +patternProperties:
>>>> +  "^r5f-[a-f0-9]+$":
>>>> +    type: object
>>>> +    description: |
>>>> +      The RPU is located in the Low Power Domain of the Processor Subsystem.
>>>> +      Each processor includes separate L1 instruction and data caches and
>>>> +      tightly coupled memories (TCM). System memory is cacheable, but the TCM
>>>> +      memory space is non-cacheable.
>>>> +
>>>> +      Each RPU contains one 64KB memory and two 32KB memories that
>>>> +      are accessed via the TCM A and B port interfaces, for a total of 128KB
>>>> +      per processor. In lock-step mode, the processor has access to 256KB of
>>>> +      TCM memory.
>>>> +
>>>> +    properties:
>>>> +      compatible:
>>>> +        const: xlnx,zynqmp-r5f
>>>> +
>>>> +      power-domains:
>>>> +        description: RPU core PM domain specifier
>>>> +        maxItems: 1
>>>> +
>>>> +      mboxes:
>>>> +        minItems: 1
>>>> +        items:
>>>> +          - description: mailbox channel to send data to RPU
>>>> +          - description: mailbox channel to receive data from RPU
>>>> +
>>>> +      mbox-names:
>>>> +        minItems: 1
>>>> +        items:
>>>> +          - const: tx
>>>> +          - const: rx
>>>> +
>>>> +      sram:
>>>> +        $ref: /schemas/types.yaml#/definitions/phandle-array
>>>> +        maxItems: 8
>>> minItems: 1
>>> maxItems: 8
>>> items:
>>>     maxItems: 1
>> I have posted v7 which adds "minItems: 1".
>>
>> However, I didn't get items: part. Is it required to have items: now?
> Yes.
>> Can I add items: part once TCM bindings are posted?
> No.
>
>> I understand that minItems and maxItems under sram property decides how many
>> phandles sram can have.
>>
>> However, maxItems: 1 under items: field what it describes?
> 'phandle-array' is really a matrix type because we can have phandles
> plus argument cells. So you have to define each of the 1-8 entries is a
> single phandle cell (and no arg cells).

Thanks for explanation. I will send new revision as suggested.

>
> Rob

Patch

diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
new file mode 100644
index 000000000000..cbff1c201a89
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml
@@ -0,0 +1,129 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx R5F processor subsystem
+
+maintainers:
+  - Ben Levinsky <[e-mail]>
+  - Tanmay Shah <[e-mail]>
+
+description: |
+  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
+  real-time processing based on the Cortex-R5F processor core from ARM.
+  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
+  floating-point unit that implements the Arm VFPv3 instruction set.
+
+properties:
+  compatible:
+    const: xlnx,zynqmp-r5fss
+
+  xlnx,cluster-mode:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2]
+    description: |
+      The RPU MPCore can operate in split mode(Dual-processor performance), Safety
+      lock-step mode(Both RPU cores execute the same code in lock-step,
+      clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while
+      core 1 runs normally). The processor does not support dynamic configuration.
+      Switching between modes is only permitted immediately after a processor reset.
+      If set to  1 then lockstep mode and if 0 then split mode.
+      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
+
+patternProperties:
+  "^r5f-[a-f0-9]+$":
+    type: object
+    description: |
+      The RPU is located in the Low Power Domain of the Processor Subsystem.
+      Each processor includes separate L1 instruction and data caches and
+      tightly coupled memories (TCM). System memory is cacheable, but the TCM
+      memory space is non-cacheable.
+
+      Each RPU contains one 64KB memory and two 32KB memories that
+      are accessed via the TCM A and B port interfaces, for a total of 128KB
+      per processor. In lock-step mode, the processor has access to 256KB of
+      TCM memory.
+
+    properties:
+      compatible:
+        const: xlnx,zynqmp-r5f
+
+      power-domains:
+        description: RPU core PM domain specifier
+        maxItems: 1
+
+      mboxes:
+        minItems: 1
+        items:
+          - description: mailbox channel to send data to RPU
+          - description: mailbox channel to receive data from RPU
+
+      mbox-names:
+        minItems: 1
+        items:
+          - const: tx
+          - const: rx
+
+      sram:
+        $ref: /schemas/types.yaml#/definitions/phandle-array
+        maxItems: 8
+        description: |
+          phandles to one or more reserved on-chip SRAM regions. Other than TCM,
+          the RPU can execute instructions and access data from, the OCM memory,
+          the main DDR memory, and other system memories.
+
+          The regions should be defined as child nodes of the respective SRAM
+          node, and should be defined as per the generic bindings in,
+          Documentation/devicetree/bindings/sram/sram.yaml
+
+      memory-region:
+        description: |
+          List of phandles to the reserved memory regions associated with the
+          remoteproc device. This is variable and describes the memories shared with
+          the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
+          vrings, ...). This reserved memory region will be allocated on DDR memory.
+        minItems: 1
+        maxItems: 8
+        items:
+          - description: region used for RPU firmware image section
+          - description: vdev buffer
+          - description: vring0
+          - description: vring1
+        additionalItems: true
+
+    required:
+      - compatible
+      - power-domains
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    r5fss: r5fss {
+        compatible = "xlnx,zynqmp-r5fss";
+        xlnx,cluster-mode = <1>;
+
+        r5f-0 {
+            compatible = "xlnx,zynqmp-r5f";
+            power-domains = <&zynqmp_firmware 0x7>;
+            memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
+            mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
+            mbox-names = "tx", "rx";
+        };
+
+        r5f-1 {
+            compatible = "xlnx,zynqmp-r5f";
+            power-domains = <&zynqmp_firmware 0x8>;
+            memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
+            mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
+            mbox-names = "tx", "rx";
+        };
+    };
+...
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
index 0d9a412fd5e0..618024cbb20d 100644
--- a/include/dt-bindings/power/xlnx-zynqmp-power.h
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -6,6 +6,12 @@ 
 #ifndef _DT_BINDINGS_ZYNQMP_POWER_H
 #define _DT_BINDINGS_ZYNQMP_POWER_H
 
+#define		PD_RPU_0	7
+#define		PD_RPU_1	8
+#define		PD_R5_0_ATCM	15
+#define		PD_R5_0_BTCM	16
+#define		PD_R5_1_ATCM	17
+#define		PD_R5_1_BTCM	18
 #define		PD_USB_0	22
 #define		PD_USB_1	23
 #define		PD_TTC_0	24