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Tue, 31 May 2022 16:44:41 -0700 Envelope-to: openamp-system-reference@lists.openampproject.org, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Received: from [172.19.3.14] (port=48904 helo=xsjtanmays50.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nwBXU-0006jm-UL; Tue, 31 May 2022 16:44:40 -0700 From: Tanmay Shah To: , , , , , , , CC: , , , Subject: [PATCH v6 2/6] arm64: dts: xilinx: zynqmp: Add RPU subsystem device node Date: Tue, 31 May 2022 16:43:06 -0700 Message-ID: <20220531234308.3317795-3-tanmay.shah@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220531234308.3317795-1-tanmay.shah@xilinx.com> References: <20220531234308.3317795-1-tanmay.shah@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0c2de73c-4f88-4137-c6c3-08da435f886e X-MS-TrafficTypeDiagnostic: BL0PR02MB5699:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2022 23:44:41.5480 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c2de73c-4f88-4137-c6c3-08da435f886e X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT037.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB5699 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org RPU subsystem can be configured in cluster-mode or split mode. Also each r5 core has separate power domains. Signed-off-by: Tanmay Shah --- Changes in v6: - None Changes in v5: - Remove optional reg property from r5fss node - Move r5fss node out of axi node Changes in v4: - Add reserved memory region node and use it in RPU subsystem node Changes in v3: - Fix checkpatch.pl style warning arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index c715a18368c2..e8315a4f7f61 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -100,6 +100,22 @@ opp03 { }; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rproc_0_fw_image: memory@3ed00000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + + rproc_1_fw_image: memory@3ef00000 { + no-map; + reg = <0x0 0x3ef00000 0x0 0x40000>; + }; + }; + zynqmp_ipi: zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; @@ -203,6 +219,23 @@ fpga_full: fpga-full { ranges; }; + r5fss: r5fss { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + r5f_core0: r5f-0 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_0>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f_core1: r5f-1 { + compatible = "xlnx,zynqmp-r5f"; + power-domains = <&zynqmp_firmware PD_RPU_1>; + memory-region = <&rproc_1_fw_image>; + }; + }; + amba: axi { compatible = "simple-bus"; #address-cells = <2>;