@@ -65,6 +65,13 @@
#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008
#define MT8195_CORE1_WDT_CFG 0x20034
+#define MT8195_SEC_CTRL 0x85000
+#define MT8195_CORE_OFFSET_ENABLE_D BIT(13)
+#define MT8195_CORE_OFFSET_ENABLE_I BIT(12)
+#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0
+#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4
+#define MT8195_L2TCM_OFFSET 0x850d0
+
#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288
@@ -486,6 +486,9 @@ static int mt8195_scp_before_load(struct mtk_scp *scp)
static int mt8195_scp_c1_before_load(struct mtk_scp *scp)
{
+ u32 sec_ctrl;
+ struct mtk_scp *scp_c0;
+
scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0);
/* hold SCP in reset while loading FW. */
@@ -494,6 +497,30 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *scp)
/* enable MPU for all memory regions */
writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF);
+ /*
+ * The L2TCM_OFFSET_RANGE and L2TCM_OFFSET shift the destination address
+ * on SRAM when SCP core 1 accesses SRAM.
+ *
+ * This configuration solves booting the SCP core 0 and core 1 from
+ * different SRAM address because core 0 and core 1 both boot from
+ * the head of SRAM by default. this must be configured before boot SCP core 1.
+ *
+ * The value of L2TCM_OFFSET_RANGE is from the viewpoint of SCP core 1.
+ * When SCP core 1 issues address within the range (L2TCM_OFFSET_RANGE),
+ * the address will be added with a fixed offset (L2TCM_OFFSET) on the bus.
+ * The shift action is tranparent to software.
+ */
+ writel(0, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW);
+ writel(scp->sram_size, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH);
+
+ scp_c0 = list_first_entry(scp->cluster, struct mtk_scp, elem);
+ writel(scp->sram_phys - scp_c0->sram_phys, scp->reg_base + MT8195_L2TCM_OFFSET);
+
+ /* enable SRAM offset when fetching instruction and data */
+ sec_ctrl = readl(scp->reg_base + MT8195_SEC_CTRL);
+ sec_ctrl |= MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D;
+ writel(sec_ctrl, scp->reg_base + MT8195_SEC_CTRL);
+
return 0;
}