| Message ID | 20240219174437.3722620-3-tanmay.shah@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | add zynqmp TCM bindings | expand |
Hi Krzysztof, Ping for reviews. Also have question. I am referring this patch from patchwork link: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240219174437.3722620-8-tanmay.shah@amd.com/ Patchwork shows that dtbs-check was failed, but I am sending dts changes in next patch. So dtbs-check failure only with bindings patch is expected. How to resolve this? Should I send dtb changes same as bindings? Or we can ignore dtbs-check errors for now? Thanks, Tanmay On 2/19/24 11:44 AM, Tanmay Shah wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Introduce bindings for TCM memory address space on AMD-xilinx Zynq > UltraScale+ platform. It will help in defining TCM in device-tree > and make it's access platform agnostic and data-driven. > > Tightly-coupled memories(TCMs) are low-latency memory that provides > predictable instruction execution and predictable data load/store > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory > banks on the ATCM and BTCM ports, for a total of 128 KB of memory. > > The TCM resources(reg, reg-names and power-domain) are documented for > each TCM in the R5 node. The reg and reg-names are made as required > properties as we don't want to hardcode TCM addresses for future > platforms and for zu+ legacy implementation will ensure that the > old dts w/o reg/reg-names works and stable ABI is maintained. > > It also extends the examples for TCM split and lockstep modes. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> > --- > > Changes in v11: > - Fix yamllint warning and reduce indentation as needed > > .../remoteproc/xlnx,zynqmp-r5fss.yaml | 192 ++++++++++++++++-- > 1 file changed, 170 insertions(+), 22 deletions(-) > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > index 78aac69f1060..77030edf41fa 100644 > --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > @@ -20,9 +20,21 @@ properties: > compatible: > const: xlnx,zynqmp-r5fss > > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: > + description: | > + Standard ranges definition providing address translations for > + local R5F TCM address spaces to bus addresses. > + > xlnx,cluster-mode: > $ref: /schemas/types.yaml#/definitions/uint32 > enum: [0, 1, 2] > + default: 1 > description: | > The RPU MPCore can operate in split mode (Dual-processor performance), Safety > lock-step mode(Both RPU cores execute the same code in lock-step, > @@ -37,7 +49,7 @@ properties: > 2: single cpu mode > > patternProperties: > - "^r5f-[a-f0-9]+$": > + "^r5f@[0-9a-f]+$": > type: object > description: | > The RPU is located in the Low Power Domain of the Processor Subsystem. > @@ -54,9 +66,6 @@ patternProperties: > compatible: > const: xlnx,zynqmp-r5f > > - power-domains: > - maxItems: 1 > - > mboxes: > minItems: 1 > items: > @@ -101,35 +110,174 @@ patternProperties: > > required: > - compatible > - - power-domains > > - unevaluatedProperties: false > +allOf: > + - if: > + properties: > + xlnx,cluster-mode: > + enum: > + - 1 > + then: > + patternProperties: > + "^r5f@[0-9a-f]+$": > + type: object > + > + properties: > + reg: > + minItems: 1 > + items: > + - description: ATCM internal memory > + - description: BTCM internal memory > + - description: extra ATCM memory in lockstep mode > + - description: extra BTCM memory in lockstep mode > + > + reg-names: > + minItems: 1 > + items: > + - const: atcm0 > + - const: btcm0 > + - const: atcm1 > + - const: btcm1 > + > + power-domains: > + minItems: 2 > + maxItems: 5 > + > + required: > + - reg > + - reg-names > + - power-domains > + > + else: > + patternProperties: > + "^r5f@[0-9a-f]+$": > + type: object > + > + properties: > + reg: > + minItems: 1 > + items: > + - description: ATCM internal memory > + - description: BTCM internal memory > + > + reg-names: > + minItems: 1 > + items: > + - const: atcm0 > + - const: btcm0 > + > + power-domains: > + minItems: 2 > + maxItems: 3 > + > + required: > + - reg > + - reg-names > + - power-domains > > required: > - compatible > + - "#address-cells" > + - "#size-cells" > + - ranges > > additionalProperties: false > > examples: > - | > - remoteproc { > - compatible = "xlnx,zynqmp-r5fss"; > - xlnx,cluster-mode = <1>; > - > - r5f-0 { > - compatible = "xlnx,zynqmp-r5f"; > - power-domains = <&zynqmp_firmware 0x7>; > - memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; > - mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; > - mbox-names = "tx", "rx"; > + #include <dt-bindings/power/xlnx-zynqmp-power.h> > + > + // Split mode configuration > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + remoteproc@ffe00000 { > + compatible = "xlnx,zynqmp-r5fss"; > + xlnx,cluster-mode = <0>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, > + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, > + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, > + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; > + > + r5f@0 { > + compatible = "xlnx,zynqmp-r5f"; > + reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; > + reg-names = "atcm0", "btcm0"; > + power-domains = <&zynqmp_firmware PD_RPU_0>, > + <&zynqmp_firmware PD_R5_0_ATCM>, > + <&zynqmp_firmware PD_R5_0_BTCM>; > + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, > + <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; > + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; > + mbox-names = "tx", "rx"; > + }; > + > + r5f@1 { > + compatible = "xlnx,zynqmp-r5f"; > + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; > + reg-names = "atcm0", "btcm0"; > + power-domains = <&zynqmp_firmware PD_RPU_1>, > + <&zynqmp_firmware PD_R5_1_ATCM>, > + <&zynqmp_firmware PD_R5_1_BTCM>; > + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, > + <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; > + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; > + mbox-names = "tx", "rx"; > + }; > }; > + }; > + > + - | > + //Lockstep configuration > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + remoteproc@ffe00000 { > + compatible = "xlnx,zynqmp-r5fss"; > + xlnx,cluster-mode = <1>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, > + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, > + <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, > + <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; > + > + r5f@0 { > + compatible = "xlnx,zynqmp-r5f"; > + reg = <0x0 0x0 0x0 0x10000>, > + <0x0 0x20000 0x0 0x10000>, > + <0x0 0x10000 0x0 0x10000>, > + <0x0 0x30000 0x0 0x10000>; > + reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; > + power-domains = <&zynqmp_firmware PD_RPU_0>, > + <&zynqmp_firmware PD_R5_0_ATCM>, > + <&zynqmp_firmware PD_R5_0_BTCM>, > + <&zynqmp_firmware PD_R5_1_ATCM>, > + <&zynqmp_firmware PD_R5_1_BTCM>; > + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, > + <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; > + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; > + mbox-names = "tx", "rx"; > + }; > > - r5f-1 { > - compatible = "xlnx,zynqmp-r5f"; > - power-domains = <&zynqmp_firmware 0x8>; > - memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; > - mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; > - mbox-names = "tx", "rx"; > + r5f@1 { > + compatible = "xlnx,zynqmp-r5f"; > + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; > + reg-names = "atcm0", "btcm0"; > + power-domains = <&zynqmp_firmware PD_RPU_1>, > + <&zynqmp_firmware PD_R5_1_ATCM>, > + <&zynqmp_firmware PD_R5_1_BTCM>; > + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, > + <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; > + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; > + mbox-names = "tx", "rx"; > + }; > }; > }; > ...
On 19/02/2024 18:44, Tanmay Shah wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Introduce bindings for TCM memory address space on AMD-xilinx Zynq > UltraScale+ platform. It will help in defining TCM in device-tree > and make it's access platform agnostic and data-driven. > > Tightly-coupled memories(TCMs) are low-latency memory that provides > predictable instruction execution and predictable data load/store > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory > banks on the ATCM and BTCM ports, for a total of 128 KB of memory. > > The TCM resources(reg, reg-names and power-domain) are documented for > each TCM in the R5 node. The reg and reg-names are made as required > properties as we don't want to hardcode TCM addresses for future > platforms and for zu+ legacy implementation will ensure that the > old dts w/o reg/reg-names works and stable ABI is maintained. > > It also extends the examples for TCM split and lockstep modes. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> > --- > > Changes in v11: > - Fix yamllint warning and reduce indentation as needed > > .../remoteproc/xlnx,zynqmp-r5fss.yaml | 192 ++++++++++++++++-- > 1 file changed, 170 insertions(+), 22 deletions(-) > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > index 78aac69f1060..77030edf41fa 100644 > --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > @@ -20,9 +20,21 @@ properties: > compatible: > const: xlnx,zynqmp-r5fss > > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 > + > + ranges: > + description: | > + Standard ranges definition providing address translations for > + local R5F TCM address spaces to bus addresses. > + > xlnx,cluster-mode: > $ref: /schemas/types.yaml#/definitions/uint32 > enum: [0, 1, 2] > + default: 1 > description: | > The RPU MPCore can operate in split mode (Dual-processor performance), Safety > lock-step mode(Both RPU cores execute the same code in lock-step, > @@ -37,7 +49,7 @@ properties: > 2: single cpu mode > > patternProperties: > - "^r5f-[a-f0-9]+$": > + "^r5f@[0-9a-f]+$": > type: object > description: | > The RPU is located in the Low Power Domain of the Processor Subsystem. > @@ -54,9 +66,6 @@ patternProperties: > compatible: > const: xlnx,zynqmp-r5f > > - power-domains: > - maxItems: 1 Why power-domains are being dropped? This should have widest constraints if you later customize it. > - > mboxes: > minItems: 1 > items: > @@ -101,35 +110,174 @@ patternProperties: > > required: > - compatible > - - power-domains Don't drop power domains. > > - unevaluatedProperties: false > +allOf: allOf block goes after required: > + - if: > + properties: > + xlnx,cluster-mode: > + enum: > + - 1 > + then: > + patternProperties: > + "^r5f@[0-9a-f]+$": > + type: object > + > + properties: > + reg: reg is missing in your patternProperties earlier. Best regards, Krzysztof
Thanks for reviews. Ack to all comments, I will address in next revision. Tanmay On 2/29/24 3:59 AM, Krzysztof Kozlowski wrote: > On 19/02/2024 18:44, Tanmay Shah wrote: > > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > > > Introduce bindings for TCM memory address space on AMD-xilinx Zynq > > UltraScale+ platform. It will help in defining TCM in device-tree > > and make it's access platform agnostic and data-driven. > > > > Tightly-coupled memories(TCMs) are low-latency memory that provides > > predictable instruction execution and predictable data load/store > > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory > > banks on the ATCM and BTCM ports, for a total of 128 KB of memory. > > > > The TCM resources(reg, reg-names and power-domain) are documented for > > each TCM in the R5 node. The reg and reg-names are made as required > > properties as we don't want to hardcode TCM addresses for future > > platforms and for zu+ legacy implementation will ensure that the > > old dts w/o reg/reg-names works and stable ABI is maintained. > > > > It also extends the examples for TCM split and lockstep modes. > > > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> > > --- > > > > Changes in v11: > > - Fix yamllint warning and reduce indentation as needed > > > > .../remoteproc/xlnx,zynqmp-r5fss.yaml | 192 ++++++++++++++++-- > > 1 file changed, 170 insertions(+), 22 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > > index 78aac69f1060..77030edf41fa 100644 > > --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml > > @@ -20,9 +20,21 @@ properties: > > compatible: > > const: xlnx,zynqmp-r5fss > > > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > + > > + ranges: > > + description: | > > + Standard ranges definition providing address translations for > > + local R5F TCM address spaces to bus addresses. > > + > > xlnx,cluster-mode: > > $ref: /schemas/types.yaml#/definitions/uint32 > > enum: [0, 1, 2] > > + default: 1 > > description: | > > The RPU MPCore can operate in split mode (Dual-processor performance), Safety > > lock-step mode(Both RPU cores execute the same code in lock-step, > > @@ -37,7 +49,7 @@ properties: > > 2: single cpu mode > > > > patternProperties: > > - "^r5f-[a-f0-9]+$": > > + "^r5f@[0-9a-f]+$": > > type: object > > description: | > > The RPU is located in the Low Power Domain of the Processor Subsystem. > > @@ -54,9 +66,6 @@ patternProperties: > > compatible: > > const: xlnx,zynqmp-r5f > > > > - power-domains: > > - maxItems: 1 > > Why power-domains are being dropped? This should have widest constraints > if you later customize it. > > > - > > mboxes: > > minItems: 1 > > items: > > @@ -101,35 +110,174 @@ patternProperties: > > > > required: > > - compatible > > - - power-domains > > Don't drop power domains. > > > > > > - unevaluatedProperties: false > > +allOf: > > allOf block goes after required: > > > + - if: > > + properties: > > + xlnx,cluster-mode: > > + enum: > > + - 1 > > + then: > > + patternProperties: > > + "^r5f@[0-9a-f]+$": > > + type: object > > + > > + properties: > > + reg: > > reg is missing in your patternProperties earlier. > > > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml index 78aac69f1060..77030edf41fa 100644 --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml @@ -20,9 +20,21 @@ properties: compatible: const: xlnx,zynqmp-r5fss + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: + description: | + Standard ranges definition providing address translations for + local R5F TCM address spaces to bus addresses. + xlnx,cluster-mode: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2] + default: 1 description: | The RPU MPCore can operate in split mode (Dual-processor performance), Safety lock-step mode(Both RPU cores execute the same code in lock-step, @@ -37,7 +49,7 @@ properties: 2: single cpu mode patternProperties: - "^r5f-[a-f0-9]+$": + "^r5f@[0-9a-f]+$": type: object description: | The RPU is located in the Low Power Domain of the Processor Subsystem. @@ -54,9 +66,6 @@ patternProperties: compatible: const: xlnx,zynqmp-r5f - power-domains: - maxItems: 1 - mboxes: minItems: 1 items: @@ -101,35 +110,174 @@ patternProperties: required: - compatible - - power-domains - unevaluatedProperties: false +allOf: + - if: + properties: + xlnx,cluster-mode: + enum: + - 1 + then: + patternProperties: + "^r5f@[0-9a-f]+$": + type: object + + properties: + reg: + minItems: 1 + items: + - description: ATCM internal memory + - description: BTCM internal memory + - description: extra ATCM memory in lockstep mode + - description: extra BTCM memory in lockstep mode + + reg-names: + minItems: 1 + items: + - const: atcm0 + - const: btcm0 + - const: atcm1 + - const: btcm1 + + power-domains: + minItems: 2 + maxItems: 5 + + required: + - reg + - reg-names + - power-domains + + else: + patternProperties: + "^r5f@[0-9a-f]+$": + type: object + + properties: + reg: + minItems: 1 + items: + - description: ATCM internal memory + - description: BTCM internal memory + + reg-names: + minItems: 1 + items: + - const: atcm0 + - const: btcm0 + + power-domains: + minItems: 2 + maxItems: 3 + + required: + - reg + - reg-names + - power-domains required: - compatible + - "#address-cells" + - "#size-cells" + - ranges additionalProperties: false examples: - | - remoteproc { - compatible = "xlnx,zynqmp-r5fss"; - xlnx,cluster-mode = <1>; - - r5f-0 { - compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware 0x7>; - memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; - mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; - mbox-names = "tx", "rx"; + #include <dt-bindings/power/xlnx-zynqmp-power.h> + + // Split mode configuration + soc { + #address-cells = <2>; + #size-cells = <2>; + + remoteproc@ffe00000 { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, + <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, + <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; }; + }; + + - | + //Lockstep configuration + soc { + #address-cells = <2>; + #size-cells = <2>; + + remoteproc@ffe00000 { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, + <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x10000>, + <0x0 0x20000 0x0 0x10000>, + <0x0 0x10000 0x0 0x10000>, + <0x0 0x30000 0x0 0x10000>; + reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, + <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; - r5f-1 { - compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware 0x8>; - memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; - mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; - mbox-names = "tx", "rx"; + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, + <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; }; }; ...