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[v2,0/6] clk: renesas: r8a77990: Add Z2 clock

Message ID 20190130094029.9604-1-horms+renesas@verge.net.au (mailing list archive)
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Series clk: renesas: r8a77990: Add Z2 clock | expand

Message

Simon Horman Jan. 30, 2019, 9:40 a.m. UTC
Hi,

this series adds the R-Car E3 (r8a77990) Z2 clock as a clock
with both a fixed and variable divisor with a parent of PLL0.

In order to do so this series:

1. Parameterise Z and Z2 clock fixed divisor in shared Gen-3 CPG
   dirver code to allow fixed divisors other than 2 - the E3 Z2
   clock has a fixed divisor of 4

2. Add a quirk to shared Gen-3 CPG to allow for an alternate location
   of the FRQCRC Z2 divider bits. This alternate location is used
   by the E3.

3. Support Z and Z2 clocks with high frequency parents.
   The parent of the E3 Z2 clock, PLL0, is 4.8GHz and thus
   when expressed in HZ must be treated as a 64bit value.

4. Actually add the E3 Z2 clock

As a follow-up, as per reading the documentation, the RZ/G2E (r8a7745)
Z2 is updated to be a variable rather than fixed clock.

Changes since v1
----------------
* Define Z2 as a variable rather than fixed clock


Testing Overview
----------------

This patchset has not been tested on RZ/G2E.

This patchset has been tested on Ebisu-4D/E3 with
"[PATCH/RFT] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices"
applied on top of renesas-devel-20190128-v5.0-rc4. This allowed CPUFreq
to be successfully exercised, showing scaling of the Z2 clock as per the
results below.

This patchset was also tested for regressions Salvator-X/M3-W ES1.0.
As per the results below CPUFreq was used to show that with these
patches applied Z and Z2 clocks still scale as expected.


Patches List by Author
----------------------

Simon Horman (3):
  clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency
    parents
  [RFT] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider
  [RFT] clk: renesas: r8a7745: Implement Z2 as a variable clock

Takeshi Kihara (3):
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
  clk: renesas: rcar-gen3: Support r8a77990 Z2 clock divider
  clk: renesas: r8a77990: Add Z2 clock

 drivers/clk/renesas/r8a7745-cpg-mssr.c  |  2 +-
 drivers/clk/renesas/r8a774a1-cpg-mssr.c |  4 ++--
 drivers/clk/renesas/r8a7795-cpg-mssr.c  |  5 +++--
 drivers/clk/renesas/r8a7796-cpg-mssr.c  |  5 +++--
 drivers/clk/renesas/r8a77965-cpg-mssr.c |  2 +-
 drivers/clk/renesas/r8a77990-cpg-mssr.c |  1 +
 drivers/clk/renesas/rcar-gen3-cpg.c     | 38 +++++++++++++++++++++++++--------
 drivers/clk/renesas/rcar-gen3-cpg.h     |  4 ++++
 8 files changed, 44 insertions(+), 17 deletions(-)