| Message ID | 20190131094021.3092-1-horms+renesas@verge.net.au (mailing list archive) |
|---|---|
| Headers | show |
| Series | clk: renesas: r8a77990: Add Z2 clock | expand |
Hi Simon, On Thu, Jan 31, 2019 at 10:40 AM Simon Horman <horms+renesas@verge.net.au> wrote: > this series adds the R-Car E3 (r8a77990) Z2 clock as a clock > with both a fixed and variable divisor with a parent of PLL0. > > In order to do so this series: > > 1. Parameterise Z and Z2 clock fixed divisor in shared Gen-3 CPG > driver code to allow fixed divisors other than 2 - the E3 Z2 > clock has a fixed divisor of 4 > > 2. Parameterise offset of Z and Z2 clock controll bits - > the offsets on E3 differ to other R-Car Gen 3 SoCs > > 3. Support Z and Z2 clocks with high frequency parents. > The parent of the E3 Z2 clock, PLL0, is 4.8GHz and thus > when expressed in HZ must be treated as a 64bit value. > > 4. Actually add the E3 Z2 clock > > As a follow-up, as per reading the documentation, the RZ/G2E (r8a774c0) > Z2 clock is added. Thanks, this looks good to me. Before queuing in clk-renesas-v5.1, to allow more testing, I'm importing this into a topic branch, to be included in today's renesas-drivers release. Gr{oetje,eeting}s, Geert
Hi, this series adds the R-Car E3 (r8a77990) Z2 clock as a clock with both a fixed and variable divisor with a parent of PLL0. In order to do so this series: 1. Parameterise Z and Z2 clock fixed divisor in shared Gen-3 CPG driver code to allow fixed divisors other than 2 - the E3 Z2 clock has a fixed divisor of 4 2. Parameterise offset of Z and Z2 clock controll bits - the offsets on E3 differ to other R-Car Gen 3 SoCs 3. Support Z and Z2 clocks with high frequency parents. The parent of the E3 Z2 clock, PLL0, is 4.8GHz and thus when expressed in HZ must be treated as a 64bit value. 4. Actually add the E3 Z2 clock As a follow-up, as per reading the documentation, the RZ/G2E (r8a774c0) Z2 clock is added. Changes since v2 ---------------- * Parameterise control bit offset rather than using a quirk * Revised RZ/G2E patch - I was confused and updating the file for the wrong part number Testing Overview ---------------- This patchset has not been tested on RZ/G2E. This patchset has been tested on Ebisu-4D/E3 with "[PATCH/RFT] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices" applied on top of renesas-devel-20190128-v5.0-rc4. This allowed CPUFreq to be successfully exercised, showing scaling of the Z2 clock as per the results below. This patchset was also tested for regressions Salvator-X/M3-W ES1.0. As per the results below CPUFreq was used to show that with these patches applied Z and Z2 clocks still scale as expected. Patches List by Author ---------------------- Simon Horman (3): clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents [RFT] clk: renesas: r8a774c0: Add Z2 clock Takeshi Kihara (2): clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor clk: renesas: r8a77990: Add Z2 clock drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 + drivers/clk/renesas/r8a7795-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a7796-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +- drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 + drivers/clk/renesas/rcar-gen3-cpg.c | 26 ++++++++++++-------------- drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++ 8 files changed, 27 insertions(+), 21 deletions(-)