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[v3,0/6] pinctrl: renesas: basic R8A779A0 (V3U) support

Message ID 20210112165912.30876-1-uli+renesas@fpond.eu (mailing list archive)
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Series pinctrl: renesas: basic R8A779A0 (V3U) support | expand


Ulrich Hecht Jan. 12, 2021, 4:59 p.m. UTC

This series provides basic V3U pin control support, up to and including the
SCIF pins.

This revision includes yet more fixes for issues found by Geert in his
review. It also adds DT bindings and Reviewed-by/Tested-by tags where
appropriate; see below for details.

Thanks to Geert and Wolfram for review and testing!


Changes since v2:
- pinctrl.c: fix signedness of lower_voltage
- use SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 where applicable
- sh_pfc.h: use PORT_GP_CFG_2 where appropriate
- sh_pfc.h: document changed unlock_reg behavior
- pfc-r8a779a0.c: fix table alignment issues
- pfc-r8a779a0.c: fix imprecise pin names in comments
- pfc-r8a779a0.c: remove redundant initializations
- add DT bindings (DT node sold separately)
- add Reviewed-by/Tested-by tags where applicable

Changes since v1:
- add support for different voltage levels
- add more PORT_GP_CFG_{2,31} macros
- add non-GP pins
- add A/B pins/groups for TCLK{1,2}, {RX,TX}1, FXR_TXDA, RXDA_EXTFXR
- add SEL_I2C*_0 to MOD_SEL2
- add PINMUX_PHYS, fix multiplexing of S{DA,CL}[0-6]
- remove undocumented POC3
- add human-readable pin names to pinmux_bias_regs[]
- use generic rcar_pinmux_{get,set}_bias() ops
- tweak coding style and commit messages
- add Reviewed-Bys where applicable

Ulrich Hecht (6):
  pinctrl: renesas: implement unlock register masks
  pinctrl: renesas: add I/O voltage level flag
  pinctrl: renesas: add PORT_GP_CFG_{2,31} macros
  pinctrl: renesas: Initial R8A779A0 (V3U) PFC support
  pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions
  dt-bindings: pinctrl: sh-pfc: Document r8a779a0 PFC support

 .../bindings/pinctrl/renesas,pfc.yaml         |    1 +
 drivers/pinctrl/renesas/Kconfig               |    5 +
 drivers/pinctrl/renesas/Makefile              |    1 +
 drivers/pinctrl/renesas/core.c                |   34 +-
 drivers/pinctrl/renesas/pfc-r8a779a0.c        | 2672 +++++++++++++++++
 drivers/pinctrl/renesas/pinctrl.c             |   16 +-
 drivers/pinctrl/renesas/sh_pfc.h              |   28 +-
 7 files changed, 2740 insertions(+), 17 deletions(-)
 create mode 100644 drivers/pinctrl/renesas/pfc-r8a779a0.c


Geert Uytterhoeven Jan. 13, 2021, 1:37 p.m. UTC | #1
On Tue, Jan 12, 2021 at 5:59 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This patch adds initial pinctrl support for the R8A779A0 (V3U) SoC,
> including bias, drive strength and voltage control.
> Based on patch by LUU HOAI <hoai.luu.ub@renesas.com>.
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl-for-v5.12.