From patchwork Tue May 10 11:06:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12844844 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78F86C433FE for ; Tue, 10 May 2022 11:08:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240678AbiEJLL4 (ORCPT ); Tue, 10 May 2022 07:11:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240697AbiEJLK7 (ORCPT ); Tue, 10 May 2022 07:10:59 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EC3A171A28; Tue, 10 May 2022 04:07:00 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,214,1647270000"; d="scan'208";a="120516019" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 10 May 2022 20:06:59 +0900 Received: from localhost.localdomain (unknown [10.226.92.112]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9A69B432529D; Tue, 10 May 2022 20:06:56 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Prabhakar Mahadev Lad Subject: [PATCH 0/2] Add GPT and POEG clock and reset entries Date: Tue, 10 May 2022 12:06:51 +0100 Message-Id: <20220510110653.7326-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This patch series aims to add GPT and POEG clock and reset entries to RZ/G2L CPG driver. Biju Das (2): clk: renesas: r9a07g044: Add GPT clock and reset entry clk: renesas: r9a07g044: Add POEG clock and reset entries drivers/clk/renesas/r9a07g044-cpg.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)