From patchwork Tue May 10 14:42:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 12845103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2ACDAC4332F for ; Tue, 10 May 2022 15:08:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241510AbiEJPLm (ORCPT ); Tue, 10 May 2022 11:11:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345738AbiEJPLG (ORCPT ); Tue, 10 May 2022 11:11:06 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6522317B60E; Tue, 10 May 2022 07:43:07 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,214,1647270000"; d="scan'208";a="120532087" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 10 May 2022 23:43:06 +0900 Received: from localhost.localdomain (unknown [10.226.92.112]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id E6F7240065BD; Tue, 10 May 2022 23:43:01 +0900 (JST) From: Biju Das To: Thierry Reding , Lee Jones , Rob Herring , Krzysztof Kozlowski , Philipp Zabel Cc: Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Biju Das , Prabhakar Mahadev Lad , linux-renesas-soc@vger.kernel.org Subject: [PATCH 0/2] Add support for RZ/G2L GPT Date: Tue, 10 May 2022 15:42:57 +0100 Message-Id: <20220510144259.9908-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer (GPT32E). It supports the following functions * 32 bits × 8 channels * Up-counting or down-counting (saw waves) or up/down-counting (triangle waves) for each counter. * Clock sources independently selectable for each channel * Two I/O pins per channel * Two output compare/input capture registers per channel * For the two output compare/input capture registers of each channel, four registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. * In output compare operation, buffer switching can be at crests or troughs, enabling the generation of laterally asymmetric PWM waveforms. * Registers for setting up frame cycles in each channel (with capability for generating interrupts at overflow or underflow) * Generation of dead times in PWM operation * Synchronous starting, stopping and clearing counters for arbitrary channels * Starting, stopping, clearing and up/down counters in response to input level comparison * Starting, clearing, stopping and up/down counters in response to a maximum of four external triggers * Output pin disable function by dead time error and detected short-circuits between output pins * A/D converter start triggers can be generated (GPT32E0 to GPT32E3) * Enables the noise filter for input capture and external trigger operation This patch series aims to add basic pwm support for RZ/G2L GPT driver by creating separate logical channels for each IOs. RFC->v1: * Added Description in binding patch * Removed comments from reg and clock * replaced rzg2l_gpt_write_mask()->rzg2l_gpt_modify() * Added rzg2l_gpt_read() and updated macros * Removed dtsi patches, will send it separately RFC: * https://lore.kernel.org/linux-renesas-soc/20220430075915.5036-1-biju.das.jz@bp.renesas.com/T/#t Biju Das (2): dt-bindings: pwm: Add RZ/G2L GPT binding pwm: Add support for RZ/G2L GPT .../bindings/pwm/renesas,rzg2l-gpt.yaml | 131 +++++++ drivers/pwm/Kconfig | 11 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-rzg2l-gpt.c | 355 ++++++++++++++++++ 4 files changed, 498 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml create mode 100644 drivers/pwm/pwm-rzg2l-gpt.c