| Message ID | 20220510151112.16249-1-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add RZ/G2L POEG support | expand |
On Tue, May 10, 2022 at 04:11:04PM +0100, Biju Das wrote: > The output pins of the general PWM timer (GPT) can be disabled by using > the port output enabling function for the GPT (POEG). Specifically, > either of the following ways can be used. > * Input level detection of the GTETRGA to GTETRGD pins. > * Output-disable request from the GPT. > * Register settings. > > Added RZ/G2L POEG support under driver/soc/renesas, as currently I am not sure about > the framework to be used for POEG. > > This patch series add support for controlling output disable function using sysfs. > > For output disable operation, POEG group needs to be linked with > GPT. So introduced renesas,poeg-group property in pwm for linking both GPT and > POEG devices. > > Please share your valuable comments. > > patch#3 and #4 depend upon [1] > [1] https://lore.kernel.org/linux-renesas-soc/20220510144259.9908-1-biju.das.jz@bp.renesas.com/T/#t I suggest to use the --base switch to git-format-patch for the next submission round. This way the built robots can parse this information, too. Best regards Uwe
Hi Uwe, Thanks for the feedback. > Subject: Re: [RFC 0/8] Add RZ/G2L POEG support > > On Tue, May 10, 2022 at 04:11:04PM +0100, Biju Das wrote: > > The output pins of the general PWM timer (GPT) can be disabled by > > using the port output enabling function for the GPT (POEG). > > Specifically, either of the following ways can be used. > > * Input level detection of the GTETRGA to GTETRGD pins. > > * Output-disable request from the GPT. > > * Register settings. > > > > Added RZ/G2L POEG support under driver/soc/renesas, as currently I am > > not sure about the framework to be used for POEG. > > > > This patch series add support for controlling output disable function > using sysfs. > > > > For output disable operation, POEG group needs to be linked with GPT. > > So introduced renesas,poeg-group property in pwm for linking both GPT > > and POEG devices. > > > > Please share your valuable comments. > > > > patch#3 and #4 depend upon [1] > > [1] > > https://lore.kernel.org/linux-renesas-soc/20220510144259.9908-1-biju.d > > as.jz@bp.renesas.com/T/#t > > I suggest to use the --base switch to git-format-patch for the next > submission round. This way the built robots can parse this information, > too. Agreed. Will take care this in next submission. Cheers, Biju
The output pins of the general PWM timer (GPT) can be disabled by using the port output enabling function for the GPT (POEG). Specifically, either of the following ways can be used. * Input level detection of the GTETRGA to GTETRGD pins. * Output-disable request from the GPT. * Register settings. Added RZ/G2L POEG support under driver/soc/renesas, as currently I am not sure about the framework to be used for POEG. This patch series add support for controlling output disable function using sysfs. For output disable operation, POEG group needs to be linked with GPT. So introduced renesas,poeg-group property in pwm for linking both GPT and POEG devices. Please share your valuable comments. patch#3 and #4 depend upon [1] [1] https://lore.kernel.org/linux-renesas-soc/20220510144259.9908-1-biju.das.jz@bp.renesas.com/T/#t Biju Das (8): dt-bindings: soc: renesas: Add RZ/G2L POEG binding drivers: soc: renesas: Add POEG driver support dt-bindings: pwm: rzg2l-gpt: Document renesas,poeg-group property pwm: rzg2l-gpt: Add support for linking with POEG arm64: dts: renesas: r9a07g044: Add POEG nodes arm64: dts: renesas: r9a07g054: Add POEG nodes arm64: dts: renesas: rzg2l-smarc: Enable POEGG{A,B,C,D} on carrier board arm64: dts: renesas: rzg2l-smarc: Link GPT4 with POEGGD on carrier board .../bindings/pwm/renesas,rzg2l-gpt.yaml | 8 + .../soc/renesas/renesas,rzg2l-poeg.yaml | 65 ++++++++ arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 44 ++++++ arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 44 ++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 17 ++ drivers/pwm/pwm-rzg2l-gpt.c | 59 +++++++ drivers/soc/renesas/Kconfig | 2 + drivers/soc/renesas/Makefile | 2 + drivers/soc/renesas/poeg/Kconfig | 12 ++ drivers/soc/renesas/poeg/Makefile | 2 + drivers/soc/renesas/poeg/poeg-rzg2l.c | 148 ++++++++++++++++++ 11 files changed, 403 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-poeg.yaml create mode 100644 drivers/soc/renesas/poeg/Kconfig create mode 100644 drivers/soc/renesas/poeg/Makefile create mode 100644 drivers/soc/renesas/poeg/poeg-rzg2l.c