From patchwork Sun Jun 26 00:43:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lad Prabhakar X-Patchwork-Id: 12895544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1ADFBC433EF for ; Sun, 26 Jun 2022 00:44:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233598AbiFZAoR (ORCPT ); Sat, 25 Jun 2022 20:44:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233383AbiFZAoQ (ORCPT ); Sat, 25 Jun 2022 20:44:16 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F24A413D23; Sat, 25 Jun 2022 17:44:14 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,222,1650898800"; d="scan'208";a="125658100" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 26 Jun 2022 09:44:14 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0B8314008C71; Sun, 26 Jun 2022 09:44:09 +0900 (JST) From: Lad Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC Date: Sun, 26 Jun 2022 01:43:24 +0100 Message-Id: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Hi All, This patch series adds PLIC support for Renesas RZ/Five SoC. Sending this as an RFC based on the discussion [0]. This patches have been tested with I2C and DMAC interface as these blocks have EDGE interrupts. [0] https://lore.kernel.org/linux-arm-kernel/87o80a7t2z.wl-maz@kernel.org/T/ v1-v2: * Fixed review comments pointed by Marc and Krzysztof. RFC-->v1: * Fixed review comments pointed by Rob and Geert. * Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC. RFC: https://lore.kernel.org/linux-renesas-soc/ 20220524172214.5104-2-prabhakar.mahadev-lad.rj@bp.renesas.com/T/ Cheers, Prabhakar Lad Prabhakar (2): dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC irqchip/sifive-plic: Add support for Renesas RZ/Five SoC .../sifive,plic-1.0.0.yaml | 44 ++++++++++- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++- 3 files changed, 113 insertions(+), 5 deletions(-)