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[v2,0/4] Renesas r9a06g032 clock table improvements

Message ID 20230301215520.828455-1-ralph.siemsen@linaro.org (mailing list archive)
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Series Renesas r9a06g032 clock table improvements | expand


Ralph Siemsen March 1, 2023, 9:55 p.m. UTC
This patch series makes several mostly-cosmetic changes to improve the clock
tables for the r9a06g032 (RZ/N1). They could all be squashed into a single
commit, though I kept them separate to make review easier.

The motivation for this change is to make the register/bit numbers more
explicit in the clock tables. With the existing format, these values are packed
into a u16 value, which is difficult to understand. After this patch, the
memory format remains the same, but the tables now list the register and bit
numbers explicitly. The logic which accesses these has also been made a
bit simpler to understand.

Changes in v2:
- Address reviewer comments
- Replace register shifts with multiply/divide
- Unify the reg access in clk_rdesc_{get,set}
- Restore the WARN_ON() check for clock gate
- Swap field order in struct regbit, to exactly match the u16 values

Ralph Siemsen (4):
  clk: renesas: r9a06g032: improve readability
  clk: renesas: r9a06g032: drop unused fields
  clk: renesas: r9a06g032: document structs
  clk: renesas: r9a06g032: improve clock tables

 drivers/clk/renesas/r9a06g032-clocks.c | 736 ++++++++++++++++++-------
 1 file changed, 541 insertions(+), 195 deletions(-)