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[0/4] clk: renesas: rzg2l-cpg: Refactor and simplify clock registration

Message ID 20240628131021.177866-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
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Series clk: renesas: rzg2l-cpg: Refactor and simplify clock registration | expand

Message

Lad, Prabhakar June 28, 2024, 1:10 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi,

This patch series aims to refactor and simplify the clock registration
code in the Renesas RZ/G2L CPG (Clock Pulse Generator) driver. The
changes enhance consistency, simplify function signatures, and remove
redundant parameters, thereby improving maintainability and reducing
potential for errors.

Cheers,
Prabhakar

Lad Prabhakar (4):
  clk: renesas: rzg2l-cpg: Use devres API to register clocks
  clk: renesas: rzg2l-cpg: Simplify rzg3s_cpg_div_clk_register function
  clk: renesas: rzg2l-cpg: Remove unused base pointer from
    rzg2l_cpg_sd_mux_clk_register
  clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in
    clock register functions

 drivers/clk/renesas/rzg2l-cpg.c | 53 +++++++++++++++++----------------
 1 file changed, 27 insertions(+), 26 deletions(-)