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[v3,0/2] clk: renesas: rzv2h-cpg: Add divider clock support

Message ID 20240828093822.162855-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
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Series clk: renesas: rzv2h-cpg: Add divider clock support | expand

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Lad, Prabhakar Aug. 28, 2024, 9:38 a.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series aims to add divider clock support and add clock and
reset entries for below IP blocks for RZ/V2H(P) SoC,
- GTM
- WDT
- RIIC
- SDHI

v2->v3
- Updated DDIV_DIVCTL_WEN() macro
- Introduced struct ddiv to pass divider config
- Updated DDIV_PACK() macro

v1->v2
- Updated DDIV_PACK macro to accommodate width and dropped DDIV_DIVCTL_WIDTH
- Updated DDIV_GET_* macros
- Now doing rmw as some of the DIVCTLx require it

Cheers,
Prabhakar

Lad Prabhakar (2):
  clk: renesas: rzv2h-cpg: Add support for dynamic switching divider
    clocks
  clk: renesas: r9a09g057-cpg: Add clock and reset entries for
    GTM/RIIC/SDHI/WDT

 drivers/clk/renesas/r9a09g057-cpg.c |  84 ++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.c     | 165 +++++++++++++++++++++++++++-
 drivers/clk/renesas/rzv2h-cpg.h     |  43 +++++++-
 3 files changed, 289 insertions(+), 3 deletions(-)