| Message ID | 20240904-pci-qcom-gen4-stability-v6-0-ec39f7ae3f62@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: qcom: Add 16.0 GT/s equalization and margining settings | expand |
On Wed, Sep 04, 2024 at 12:41:56PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > This series adds 16.0 GT/s specific equalization and RX lane margining settings > to the Qcom RC and EP drivers. This series is mandatory for the stable operation > of the PCIe link at 16.0 GT/s on the Qcom platforms. > Changes in v6: > > - Dropped the code refactoring patch as suggested by Johan > - Added 2 patches to fix the caching of maximum supported link speed value that > is needed to apply the equalization/margining settings > - Updated the commit message of patch 3 as per Bjorn's suggestion Thanks for the update. This series fixes the NVMe link errors on the x1e80100 CRD: Tested-by: Johan Hovold <johan+linaro@kernel.org> Johan
Hi, This series adds 16.0 GT/s specific equalization and RX lane margining settings to the Qcom RC and EP drivers. This series is mandatory for the stable operation of the PCIe link at 16.0 GT/s on the Qcom platforms. NOTE: ===== I've taken over the series from Shashank based on the discussion [1]. In order to apply the equalization/margining settings properly in the Qcom driver, I added the first 2 patches to the series which inevitably touches other vendor drivers also. - Mani Changes in v6: - Dropped the code refactoring patch as suggested by Johan - Added 2 patches to fix the caching of maximum supported link speed value that is needed to apply the equalization/margining settings - Updated the commit message of patch 3 as per Bjorn's suggestion For previous changelogs, please refer [2] [1] https://lore.kernel.org/linux-pci/af65b744-7538-4929-9ab4-8ee42e17b8d1@quicinc.com/ [2] https://lore.kernel.org/linux-pci/20240821170917.21018-1-quic_schintav@quicinc.com/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Manivannan Sadhasivam (2): PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed' PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed Shashank Babu Chinta Venkata (2): PCI: qcom: Add equalization settings for 16.0 GT/s PCI: qcom: Add RX margining settings for 16.0 GT/s MAINTAINERS | 4 +- drivers/pci/controller/dwc/Kconfig | 5 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pci-imx6.c | 8 +-- drivers/pci/controller/dwc/pcie-designware.c | 22 +++++--- drivers/pci/controller/dwc/pcie-designware.h | 32 ++++++++++- drivers/pci/controller/dwc/pcie-intel-gw.c | 4 +- drivers/pci/controller/dwc/pcie-qcom-common.c | 76 +++++++++++++++++++++++++++ drivers/pci/controller/dwc/pcie-qcom-common.h | 9 ++++ drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +++ drivers/pci/controller/dwc/pcie-qcom.c | 6 +++ drivers/pci/controller/dwc/pcie-rcar-gen4.c | 6 +-- 12 files changed, 162 insertions(+), 17 deletions(-) --- base-commit: 47ac09b91befbb6a235ab620c32af719f8208399 change-id: 20240904-pci-qcom-gen4-stability-02ec65a7e6e4 Best regards,