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Mon, 02 Dec 2024 12:39:27 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 0/2] clk: renesas: rzv2h-cpg: Add CRU and CSI clocks Date: Mon, 2 Dec 2024 20:39:14 +0000 Message-ID: <20241202203916.48668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Hi All, This patch series aims to add CRU/CSI clock and reset entries to the RZ/V2H(P) clock driver. 1] patch#1: Allows exclusion of external and specific RZ/V2H(P) clocks, such as those in CRU block, from Runtime PM using a new no_pm flag and helper function. 2] patch#2 Extends the r9a09g057 driver to include PLLVDO, its related CRU clocks (CRU0-CRU3), and corresponding reset entries. v2->v3 -> Replaced `rzv2h-cpg` to `rzv2h` in commit header -> Switched to use for loop while looping -> Considering core clocks to be non pm clocks v1->v2 - Update code to skip external clocks from runtime PM Cheers, Prabhakar Lad Prabhakar (2): clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets drivers/clk/renesas/r9a09g057-cpg.c | 45 +++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.c | 44 +++++++++++++++++++++++++--- drivers/clk/renesas/rzv2h-cpg.h | 18 ++++++++++-- 3 files changed, 100 insertions(+), 7 deletions(-)