| Message ID | 20241213123550.289193-1-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add clock driver support for Renesas RZ/G3E SoC | expand |
Hi Biju et al, On Fri, Dec 13, 2024 at 1:36 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > This patch series adds clock driver support for RZ/G3E. Also add > MSTOP support for RZ/V2H. > > This patch series is tested on renesas-devel and next. > Biju Das (3): > clk: renesas: rzv2h-cpg: Add MSTOP support > clk: renesas: rzv2h-cpg: Add support for RZ/G3E SoC > clk: renesas: r9a09g047: Add CA55 core clocks Given the issues with "[PATCH v3 1/3] clk: renesas: rzv2h-cpg: Add MSTOP support" reported by email[1] and on #renesas-soc, I think it is best not to include this patch and all other patches that depend on it in tomorrow's pull request for clk-next. That leaves us with some extra time to fix the issues. Unfortunately, I understand not all parties will have returned from holidays by the time I will send my second pull request (usually just before rc6)... [1] "[PATCH 1/5] clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling" https://lore.kernel.org/all/20241218142045.77269-2-prabhakar.mahadev-lad.rj@bp.renesas.com Gr{oetje,eeting}s, Geert
Hi all, This patch series adds clock driver support for RZ/G3E. Also add MSTOP support for RZ/V2H. This patch series is tested on renesas-devel and next. v2->v3: * Updated commit header and description for this series as all the patches accepted except clock. * Updated commit description for patch#1 as adding MSTOP support for RZ/V2H first will ease backporting. * Added missing MSTOP data for SD{0,1,2} * Replaced BUS_MSTOP_NO_DATA->BUS_MSTOP_NONE * Added idx, mask variable to struct rzv2h_mstop to simplify the code. * Started setting initial value of refcount with the correct value based on the clock's current state. * Collected tags. v1->v2: * Collected tags. * Fixed typo "CORE_CLK*"->"CORECLK*" to match with hardware manual in the clk bindings. * Added MSTOP data for RZ/V2H CRU IP. * Fixed typo clock->clk in error path of rzv2h_cpg_register_mod_clk(). * Added OPP table support for frequency scaling. Biju Das (3): clk: renesas: rzv2h-cpg: Add MSTOP support clk: renesas: rzv2h-cpg: Add support for RZ/G3E SoC clk: renesas: r9a09g047: Add CA55 core clocks drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g047-cpg.c | 116 +++++++++++++++++++++ drivers/clk/renesas/r9a09g057-cpg.c | 153 ++++++++++++++++++---------- drivers/clk/renesas/rzv2h-cpg.c | 105 ++++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 24 +++-- 6 files changed, 344 insertions(+), 62 deletions(-) create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c