[00/11] Add Support for RZ/G3E ICU

Message

Biju Das Jan. 20, 2025, 9:46 a.m. UTC

The ICU block on the RZ/G3E SoC is almost identical to the one found on
the RZ/V2H SoC, with the following differences:
 - The TINT register offset is 0x830 compared to ox30 on RZ/V2H.
 - The number of supported GPIO interrupts for TINT selection is 141
   instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 15 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Add support for the RZ/G3E ICU driver.

Biju Das (11):
  dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E
    SoC
  clk: renesas: r9a09g047: Add ICU clock/reset
  irqchip/renesas-rzv2h: Drop irqchip from struct rzv2h_icu_priv
  irqchip/renesas-rzv2h: Simplify rzv2h_icu_init()
  irqchip/renesas-rzv2h: Add struct rzv2h_hw_info with t_offs variable
  irqchip/renesas-rzv2h: Add max_tssel variable to struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add tssr_k variable to struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add tssel_mask and tssel_shift variables to
    struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add tien variable to struct rzv2h_hw_info
  irqchip/renesas-rzv2h: Add RZ/G3E support
  arm64: dts: renesas: r9a09g047: Add icu node

 .../renesas,rzv2h-icu.yaml                    |   6 +-
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 108 ++++++++++++
 drivers/clk/renesas/r9a09g047-cpg.c           |   3 +
 drivers/irqchip/irq-renesas-rzv2h.c           | 159 +++++++++++++-----
 4 files changed, 229 insertions(+), 47 deletions(-)