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Mon, 07 Apr 2025 09:52:16 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec16ba978sm139272305e9.23.2025.04.07.09.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 09:52:15 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 0/9] clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH Date: Mon, 7 Apr 2025 17:51:53 +0100 Message-ID: <20250407165202.197570-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Hi All, This patch series introduces enhancements and new features for the Renesas RZ/V2H(P) family driver and R9A09G057 SoC specific clock drivers. The changes include support for static mux clocks, static dividers, support for ignoring monitoring bits for external clocks, and improved clock state validation. Additionally, the series includes updates to device tree bindings for USB2 PHY and GBETH PTP core clocks, as well as the addition of clock and reset entries for USB2 and GBETH peripherals. @Geert, Note I've squashed the below patch series [0] and [1] into a single patch series to avoid conflicts. Patch [2] will be dropped from Biju's patch series as this is now patch 3/9. Patches are based on the v6.15-rc1 + renesas-drivers/renesas-clk-for-v6.16 branch. [0] https://lore.kernel.org/all/20250328200105.176129-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [1] https://lore.kernel.org/all/20250228202655.491035-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [2] https://lore.kernel.org/all/20250303110433.76576-3-biju.das.jz@bp.renesas.com/ v1->v2 - Added ack from Krzysztof for the dt-bindings patch. - Merged the series into a single patch series - Introduced DDIV_PACK_NO_RMW macro to support static dividers Cheers, Prabhakar Biju Das (1): clk: renesas: rzv2h-cpg: Support static dividers without RMW Lad Prabhakar (8): clk: renesas: rzv2h-cpg: Add support for static mux clocks clk: renesas: rzv2h-cpg: Add macro for defining static dividers clk: renesas: rzv2h-cpg: Use str_on_off() helper in rzv2h_mod_clock_endisable() clk: renesas: rzv2h-cpg: Use both CLK_ON and CLK_MON bits for clock state validation clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks clk: renesas: r9a09g057: Add clock and reset entries for USB2 clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1 drivers/clk/renesas/r9a09g057-cpg.c | 92 +++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.c | 65 ++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 93 ++++++++++++++++++- .../dt-bindings/clock/renesas,r9a09g057-cpg.h | 4 + 4 files changed, 244 insertions(+), 10 deletions(-)