mbox series

[v2,0/2] Add RZ/G3E XSPI clocks

Message ID 20250408113845.130950-1-biju.das.jz@bp.renesas.com (mailing list archive)
Headers show
Series Add RZ/G3E XSPI clocks | expand

Message

Biju Das April 8, 2025, 11:38 a.m. UTC 
RZ/G3E XSPI has 4 clocks{ahb, axi, spi, spix2). spi and xpix share the
same CPG_ON bit, but they have different monitor bit. Modelled clk_spi
as a fixed divider clock with parent clk_spix2 and factor two.

v1->v2:
 * Modelled clk_spi as a fixed divider clock with parent clk_spix2 and
   factor two and dropped coupled clk.
 * Updated commit description for the cover letter
 * Dropped static divider patch as it is updated as [1]
 * Updated LAST_DT_CORE_CLK macro
 * Replaced DEF_SDIV->DEF_CSDIV macro
 * Added spi_clk_spi as core clk
 * Updated CSDIV0_DIVCTL3 macro.
 * spi_clk_spix2 is handled as module clock with RPM.
 * Dropped CDDIV0_DIVCTL1 as it is already merged in clk tree.
 
Note:
 This patch series depend upon 
[1] https://lore.kernel.org/all/20250407165202.197570-4-prabhakar.mahadev-lad.rj@bp.renesas.com/
[2] https://lore.kernel.org/all/20250401143537.224047-2-biju.das.jz@bp.renesas.com/

Biju Das (2):
  clk: renesas: r9a09g047: Add support for xspi mux and divider
  clk: renesas: r9a09g047: Add XSPI clock/reset

 drivers/clk/renesas/r9a09g047-cpg.c | 39 ++++++++++++++++++++++++++++-
 drivers/clk/renesas/rzv2h-cpg.h     |  3 +++
 2 files changed, 41 insertions(+), 1 deletion(-)