From patchwork Thu Jan 21 05:09:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 8077801 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1E2269F88A for ; Thu, 21 Jan 2016 05:09:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 85B6A2053A for ; Thu, 21 Jan 2016 05:09:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C6B0B2054D for ; Thu, 21 Jan 2016 05:09:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750793AbcAUFJu (ORCPT ); Thu, 21 Jan 2016 00:09:50 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:56566 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758548AbcAUFJt (ORCPT ); Thu, 21 Jan 2016 00:09:49 -0500 Received: from reginn.isobedori.kobe.vergenet.net (p5023-ipbfp803kobeminato.hyogo.ocn.ne.jp [123.221.39.23]) by kirsty.vergenet.net (Postfix) with ESMTPA id ADDD125B81D; Thu, 21 Jan 2016 16:09:43 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1453352983; bh=io4nda4ImPAZ+BgRUSRrt6NY7pc/oM6LRIGWT2dAYsY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J+Bifb8n178gZqU/qpLy79CCJ7I+ymI3I6fVMDunRaHCKw5luQnolWzv96yncOcn+ TxEH7rPjNjRj1vm8HLkUrXWOeaO7tirZq4xrbOhA/MQJamsaJzOfLS+Xmyh7TMpFeW pO457DjJlshBT4aAOB5FLKIKt6vGdmDOCv8YKlg8= Received: by reginn.isobedori.kobe.vergenet.net (Postfix, from userid 7100) id A33529404FB; Thu, 21 Jan 2016 14:09:42 +0900 (JST) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Simon Horman , Sergei Shtylyov Subject: [PATCH 1/2] ARM: dts: r8a7793: add CAN clocks Date: Thu, 21 Jan 2016 14:09:40 +0900 Message-Id: <1453352981-16104-2-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1453352981-16104-1-git-send-email-horms+renesas@verge.net.au> References: <1453352981-16104-1-git-send-email-horms+renesas@verge.net.au> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree along with the USB_EXTAL clock from which clkp2 is derived. Based on work by Sergei Shtylyov for the r8a7791 SoC. Cc: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 0ce7cc420c9d..5d9375fa6759 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -706,12 +706,30 @@ clock-output-names = "extal"; }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "usb_extal"; + }; + + /* External CAN clock */ + can_clk: can_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "can_clk"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7793-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; + clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "z",