| Message ID | 1458251683-2061-2-git-send-email-wsa@the-dreams.de (mailing list archive) |
|---|---|
| State | RFC |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Wolfram, On Thu, Mar 17, 2016 at 10:54 PM, Wolfram Sang <wsa@the-dreams.de> wrote: > From: Wolfram Sang <wsa+renesas@sang-engineering.com> > > Hard code the RCLK to make the watchdog usable for testing. > > I am not sure where to put the selectable parent clock in DT. It can be > the internal RCLK or EXTALR. Also, the fixed divider value depends on > mode pins and should be read from the register, too. EXTALR is already in DT. I don't think we need the internal RCLK in DT. It should be handled internally in the r8a7795-cpg-mssr drivers. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
> EXTALR is already in DT.
Isn't it a board thing if EXTALR is populated?
Hi Wolfram, On Fri, Mar 18, 2016 at 10:59 AM, Wolfram Sang <wsa@the-dreams.de> wrote: >> EXTALR is already in DT. > > Isn't it a board thing if EXTALR is populated? Indeed. The CPG driver should register a MUX clock that has EXTALR and the internal RCLK as parents. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
> The CPG driver should register a MUX clock that has EXTALR and the internal > RCLK as parents. I don't think this will work. clk_mux will switch parents depending on the rate to be set up. But here we want to select one parent at boot-time (and want to stay with it). I hacked up something. Will send it in a minute so we can talk about code.
diff --git a/drivers/clk/shmobile/r8a7795-cpg-mssr.c b/drivers/clk/shmobile/r8a7795-cpg-mssr.c index b2198aef5ed429..3c10d9d11314ed 100644 --- a/drivers/clk/shmobile/r8a7795-cpg-mssr.c +++ b/drivers/clk/shmobile/r8a7795-cpg-mssr.c @@ -109,6 +109,8 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), + //FIXME: divisor depends on MD13+14. Input can be CLK_EXTALR, too. + DEF_FIXED("rclk", R8A7795_CLK_R, CLK_EXTAL, 1024, 1), DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), @@ -139,6 +141,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), + DEF_MOD("rwdt0", 402, R8A7795_CLK_R), DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
From: Wolfram Sang <wsa+renesas@sang-engineering.com> Hard code the RCLK to make the watchdog usable for testing. I am not sure where to put the selectable parent clock in DT. It can be the internal RCLK or EXTALR. Also, the fixed divider value depends on mode pins and should be read from the register, too. Not-really-Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- drivers/clk/shmobile/r8a7795-cpg-mssr.c | 3 +++ 1 file changed, 3 insertions(+)