From patchwork Thu Apr 7 12:20:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8772301 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 755F3C0553 for ; Thu, 7 Apr 2016 12:20:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D48232020F for ; Thu, 7 Apr 2016 12:20:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4F4DB20263 for ; Thu, 7 Apr 2016 12:20:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755813AbcDGMU0 (ORCPT ); Thu, 7 Apr 2016 08:20:26 -0400 Received: from andre.telenet-ops.be ([195.130.132.53]:36275 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755945AbcDGMUW (ORCPT ); Thu, 7 Apr 2016 08:20:22 -0400 Received: from ayla.of.borg ([84.195.106.123]) by andre.telenet-ops.be with bizsmtp id fQLE1s0082fm56U01QLESE; Thu, 07 Apr 2016 14:20:20 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1ao8v0-0005yf-5r; Thu, 07 Apr 2016 14:20:14 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1ao8v7-0003Se-Ca; Thu, 07 Apr 2016 14:20:21 +0200 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , Laurent Pinchart , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v4 5/7] soc: renesas: Add r8a7793 SYSC PM Domain Binding Definitions Date: Thu, 7 Apr 2016 14:20:18 +0200 Message-Id: <1460031620-13240-6-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460031620-13240-1-git-send-email-geert+renesas@glider.be> References: <1460031620-13240-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP R-Car M2-N is identical to R-Car M2-W w.r.t. power domains, so reuse the definitions from the latter. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart --- v4: - Rename R8A7793_PD_SH to R8A7793_PD_SH_4A, - Use the numbers directly, to make the header file self-contained, - Add always-on power area, v3: - New. --- include/dt-bindings/power/r8a7793-sysc.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 include/dt-bindings/power/r8a7793-sysc.h diff --git a/include/dt-bindings/power/r8a7793-sysc.h b/include/dt-bindings/power/r8a7793-sysc.h new file mode 100644 index 0000000000000000..b5693df3d830ed42 --- /dev/null +++ b/include/dt-bindings/power/r8a7793-sysc.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + * + * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. + */ + +#define R8A7793_PD_CA15_CPU0 0 +#define R8A7793_PD_CA15_CPU1 1 +#define R8A7793_PD_CA15_SCU 12 +#define R8A7793_PD_SH_4A 16 +#define R8A7793_PD_SGX 20 + +/* Always-on power area */ +#define R8A7793_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */