From patchwork Thu Apr 7 12:20:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8772601 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8ADA8C0554 for ; Thu, 7 Apr 2016 12:21:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E30E220251 for ; Thu, 7 Apr 2016 12:21:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 481D42020F for ; Thu, 7 Apr 2016 12:21:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755949AbcDGMUu (ORCPT ); Thu, 7 Apr 2016 08:20:50 -0400 Received: from albert.telenet-ops.be ([195.130.137.90]:39155 "EHLO albert.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756008AbcDGMU3 (ORCPT ); Thu, 7 Apr 2016 08:20:29 -0400 Received: from ayla.of.borg ([84.195.106.123]) by albert.telenet-ops.be with bizsmtp id fQLV1s0032fm56U06QLVwJ; Thu, 07 Apr 2016 14:20:29 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1ao8vF-0005zl-05; Thu, 07 Apr 2016 14:20:29 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1ao8vM-0003Vp-84; Thu, 07 Apr 2016 14:20:36 +0200 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Laurent Pinchart , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v4 01/12] ARM: dts: r8a7779: Add SYSC PM Domains Date: Thu, 7 Apr 2016 14:20:24 +0200 Message-Id: <1460031635-13452-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460031635-13452-1-git-send-email-geert+renesas@glider.be> References: <1460031635-13452-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a device node for the System Controller, and hook it up to the CPG/MSTP Clock Domain. Hook up ARM CPU cores 1-3 to their respective PM Domains. Note that ARM CPU core 0 cannot be shut off. Signed-off-by: Geert Uytterhoeven --- v4: - Add power-domains property to the sysc node, to refer to the SoC's Clock Domain, v3: - Drop power area hiearchy from DT, - Switch to "#power-domain-cells = <1>", v2: - Correct sysc "reg" property (#address/size-cells = 1, not 2), - Change one-line summary prefix to match current arm-soc practices, - Update compatible values. --- arch/arm/boot/dts/r8a7779.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 5c1d48d712a18652..2679ab4629d5c2b2 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { compatible = "renesas,r8a7779"; @@ -34,18 +35,21 @@ compatible = "arm,cortex-a9"; reg = <1>; clock-frequency = <1000000000>; + power-domains = <&sysc R8A7779_PD_ARM1>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; clock-frequency = <1000000000>; + power-domains = <&sysc R8A7779_PD_ARM2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; clock-frequency = <1000000000>; + power-domains = <&sysc R8A7779_PD_ARM3>; }; }; @@ -586,4 +590,11 @@ "mmc1", "mmc0"; }; }; + + sysc: system-controller@ffd85000 { + compatible = "renesas,r8a7779-sysc"; + reg = <0xffd85000 0x0200>; + power-domains = <&cpg_clocks>; + #power-domain-cells = <1>; + }; };