From patchwork Thu Apr 7 12:20:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8772371 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EC09BC0553 for ; Thu, 7 Apr 2016 12:20:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3FE142024F for ; Thu, 7 Apr 2016 12:20:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B89B920251 for ; Thu, 7 Apr 2016 12:20:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756088AbcDGMUd (ORCPT ); Thu, 7 Apr 2016 08:20:33 -0400 Received: from albert.telenet-ops.be ([195.130.137.90]:39139 "EHLO albert.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756187AbcDGMUa (ORCPT ); Thu, 7 Apr 2016 08:20:30 -0400 Received: from ayla.of.borg ([84.195.106.123]) by albert.telenet-ops.be with bizsmtp id fQLV1s0042fm56U06QLVwK; Thu, 07 Apr 2016 14:20:29 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1ao8vF-000605-4D; Thu, 07 Apr 2016 14:20:29 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1ao8vM-0003WE-CH; Thu, 07 Apr 2016 14:20:36 +0200 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Laurent Pinchart , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v4 06/12] arm64: dts: r8a7795: Add SYSC PM Domains Date: Thu, 7 Apr 2016 14:20:29 +0200 Message-Id: <1460031635-13452-7-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460031635-13452-1-git-send-email-geert+renesas@glider.be> References: <1460031635-13452-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a device node for the System Controller, and hook it up to the CPG/MSSR Clock Domain. Hook up the Cortex-A57 CPU cores and the Cortex-A57 and Cortex A53 L2 caches/SCUs to their respective PM Domains. Signed-off-by: Geert Uytterhoeven --- v4: - Add power-domains property to the sysc node, to refer to the SoC's Clock Domain, - Extract using "<&sysc R8A7795_PD_ALWAYS_ON>" for devices in the always-on power area into a separate patch, v3: - Drop power area hiearchy from DT, - Switch to "#power-domain-cells = <1>", - Use "<&sysc R8A7795_PD_ALWAYS_ON>" for devices in the always-on power area, - Drop fallback compatibility strings, v2: - New. --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 11f9971a85433b7f..89c72280f9a77403 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -10,6 +10,7 @@ #include #include +#include / { compatible = "renesas,r8a7795"; @@ -39,6 +40,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -47,6 +49,7 @@ compatible = "arm,cortex-a57","arm,armv8"; reg = <0x1>; device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -54,6 +57,7 @@ compatible = "arm,cortex-a57","arm,armv8"; reg = <0x2>; device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -61,6 +65,7 @@ compatible = "arm,cortex-a57","arm,armv8"; reg = <0x3>; device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -68,12 +73,14 @@ L2_CA57: cache-controller@0 { compatible = "cache"; + power-domains = <&sysc R8A7795_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; L2_CA53: cache-controller@1 { compatible = "cache"; + power-domains = <&sysc R8A7795_PD_CA53_SCU>; cache-unified; cache-level = <2>; }; @@ -305,6 +312,13 @@ #power-domain-cells = <0>; }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7795-sysc"; + reg = <0 0xe6180000 0 0x0400>; + power-domains = <&cpg>; + #power-domain-cells = <1>; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,rcar-dmac"; reg = <0 0xec700000 0 0x10000>;