From patchwork Wed Apr 13 14:44:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8823131 X-Patchwork-Delegate: horms@verge.net.au Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 79B38C0553 for ; Wed, 13 Apr 2016 14:45:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CC30420374 for ; Wed, 13 Apr 2016 14:45:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 264D82035D for ; Wed, 13 Apr 2016 14:45:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933947AbcDMOos (ORCPT ); Wed, 13 Apr 2016 10:44:48 -0400 Received: from albert.telenet-ops.be ([195.130.137.90]:46482 "EHLO albert.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758781AbcDMOoq (ORCPT ); Wed, 13 Apr 2016 10:44:46 -0400 Received: from ayla.of.borg ([84.195.106.123]) by albert.telenet-ops.be with bizsmtp id hqkl1s0012fm56U06qklTS; Wed, 13 Apr 2016 16:44:45 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1aqM28-0001nV-WB; Wed, 13 Apr 2016 16:44:44 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1aqM2H-0002j0-M2; Wed, 13 Apr 2016 16:44:53 +0200 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Laurent Pinchart , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v5 03/12] ARM: dts: r8a7791: Add SYSC PM Domains Date: Wed, 13 Apr 2016 16:44:43 +0200 Message-Id: <1460558692-10414-4-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460558692-10414-1-git-send-email-geert+renesas@glider.be> References: <1460558692-10414-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a device node for the System Controller. Hook up the Cortex-A15 CPU cores and the Cortex-A15 L2 cache/SCU to their respective PM Domains. Signed-off-by: Geert Uytterhoeven --- v5: - Remove "power-domains" property again from the sysc node, as the System Controller itself is not part of the Clock Domain, v4: - Add "power-domains" property to the sysc node, to refer to the SoC's Clock Domain, v3: - Drop power area hiearchy from DT, - Switch to "#power-domain-cells = <1>", - Drop fallback compatibility strings, v2: - Change one-line summary prefix to match current arm-soc practices, - Update compatible values. --- arch/arm/boot/dts/r8a7791.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 8693888057ff3f7d..cffd7f49c01fb7a1 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include / { compatible = "renesas,r8a7791"; @@ -51,6 +52,7 @@ voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7791_CLK_Z>; clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -67,6 +69,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; }; @@ -92,6 +95,7 @@ L2_CA15: cache-controller@0 { compatible = "cache"; + power-domains = <&sysc R8A7791_PD_CA15_SCU>; cache-unified; cache-level = <2>; }; @@ -1491,6 +1495,12 @@ }; }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7791-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7791", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>;