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[RFC,1/2] clk: renesas: r8a7740: add an "sd" clock

Message ID 1460897201-7184-2-git-send-email-wsa@the-dreams.de (mailing list archive)
State RFC
Delegated to: Geert Uytterhoeven
Headers show

Commit Message

Wolfram Sang April 17, 2016, 12:46 p.m. UTC 
From: Wolfram Sang <wsa+renesas@sang-engineering.com>

Create a virtual "sd" clock to feed the MSTP clocks for the SDHI cores.
MSTP clocks can change the rate of their parents which is undesired for
a generic clock as HP. So, add this static "sd" clock where the MSTP
clocks can safely connect to.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/clk-r8a7740.c | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8a7740.c
index 2f7ce6696b6c0f..29834c3f22bdea 100644
--- a/drivers/clk/renesas/clk-r8a7740.c
+++ b/drivers/clk/renesas/clk-r8a7740.c
@@ -119,6 +119,8 @@  r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
 			parent_name = "system";
 		if (!(value & BIT(6)))
 			div = 2;
+	} else if (!strcmp(name, "sd")) {
+		parent_name = "hp";
 	} else {
 		struct div4_clk *c;
 		for (c = div4_clks; c->name; c++) {