diff mbox

[v2,2/4] arm64: dts: renesas: r8a7795: Add VSP instances

Message ID 1470745752-23738-3-git-send-email-laurent.pinchart+renesas@ideasonboard.com (mailing list archive)
State Accepted
Commit 9f8573e38a0b377aa092db96be140be4d59a7fae
Delegated to: Simon Horman
Headers show

Commit Message

Laurent Pinchart Aug. 9, 2016, 12:29 p.m. UTC
The r8a7795 has 9 VSP instances.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 90 ++++++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

Comments

Geert Uytterhoeven Aug. 29, 2016, 4:12 p.m. UTC | #1
Hi Laurent,

On Tue, Aug 9, 2016 at 2:29 PM, Laurent Pinchart
<laurent.pinchart+renesas@ideasonboard.com> wrote:
> The r8a7795 has 9 VSP instances.

7?

> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 90 ++++++++++++++++++++++++++++++++
>  1 file changed, 90 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index f8b1c421e845..d9c6653471f4 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi

> @@ -1323,6 +1363,16 @@
>                         power-domains = <&sysc R8A7795_PD_A3VP>;
>                 };
>
> +               vspi2: vsp@fe9c0000 {
> +                       compatible = "renesas,vsp2";
> +                       reg = <0 0xfe9c0000 0 0x8000>;
> +                       interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 629>;
> +                       power-domains = <&sysc R8A7795_PD_A3VP>;
> +
> +                       renesas,fcp = <&fcpvi2>;
> +               };
> +
>                 fcpvi2: fcp@fe9cf000 {
>                         compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
>                         reg = <0 0xfe9cf000 0 0x200>;

> @@ -1351,6 +1431,16 @@
>                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
>                 };
>
> +               vspd3: vsp@fea38000 {
> +                       compatible = "renesas,vsp2";
> +                       reg = <0 0xfea38000 0 0x4000>;
> +                       interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 620>;
> +                       power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> +
> +                       renesas,fcp = <&fcpvd3>;
> +               };
> +

Looks like vspi2 and vspd3 are no more...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Laurent Pinchart Aug. 30, 2016, 9:36 a.m. UTC | #2
Hi Geert,

(CC'ing Morimoto-san)

On Monday 29 Aug 2016 18:12:07 Geert Uytterhoeven wrote:
> On Tue, Aug 9, 2016 at 2:29 PM, Laurent Pinchart wrote:
> > The r8a7795 has 9 VSP instances.
> 
> 7?
> 
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > 
> >  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 90 +++++++++++++++++++++++++++
> >  1 file changed, 90 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index
> > f8b1c421e845..d9c6653471f4 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > @@ -1323,6 +1363,16 @@
> >                         power-domains = <&sysc R8A7795_PD_A3VP>;
> >                 };
> > 
> > +               vspi2: vsp@fe9c0000 {
> > +                       compatible = "renesas,vsp2";
> > +                       reg = <0 0xfe9c0000 0 0x8000>;
> > +                       interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cpg CPG_MOD 629>;
> > +                       power-domains = <&sysc R8A7795_PD_A3VP>;
> > +
> > +                       renesas,fcp = <&fcpvi2>;
> > +               };
> > +
> >                 fcpvi2: fcp@fe9cf000 {
> >                         compatible = "renesas,r8a7795-fcpv",
> >                         "renesas,fcpv";
> >                         reg = <0 0xfe9cf000 0 0x200>;
> > @@ -1351,6 +1431,16 @@
> >                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> >                 };
> > 
> > +               vspd3: vsp@fea38000 {
> > +                       compatible = "renesas,vsp2";
> > +                       reg = <0 0xfea38000 0 0x4000>;
> > +                       interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cpg CPG_MOD 620>;
> > +                       power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> > +
> > +                       renesas,fcp = <&fcpvd3>;
> > +               };
> > +
> 
> Looks like vspi2 and vspd3 are no more...

What the f... The latest errata agrees with you, and if the documentation is 
indeed correct, that's a completely brain-dead design change. I have no idea 
how the DU is supposed to be used if both DU0 and DU3 are connected to the 
same VSP (VSPD0), as mentioned in the latest H3 errata. Furthermore, the 
change doesn't seem to be applicable to ES1.0, as I've successfully tested the 
VGA output on my Salvator-X board, using VSPD3.

Morimoto-san, could you please try to get more information about this ?
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index f8b1c421e845..d9c6653471f4 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1274,6 +1274,16 @@ 
 			status = "disabled";
 		};
 
+		vspbc: vsp@fe920000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe920000 0 0x8000>;
+			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 624>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+
+			renesas,fcp = <&fcpvb1>;
+		};
+
 		fcpvb1: fcp@fe92f000 {
 			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
 			reg = <0 0xfe92f000 0 0x200>;
@@ -1302,6 +1312,16 @@ 
 			power-domains = <&sysc R8A7795_PD_A3VP>;
 		};
 
+		vspbd: vsp@fe960000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe960000 0 0x8000>;
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 626>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+
+			renesas,fcp = <&fcpvb0>;
+		};
+
 		fcpvb0: fcp@fe96f000 {
 			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
 			reg = <0 0xfe96f000 0 0x200>;
@@ -1309,6 +1329,16 @@ 
 			power-domains = <&sysc R8A7795_PD_A3VP>;
 		};
 
+		vspi0: vsp@fe9a0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe9a0000 0 0x8000>;
+			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 631>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+
+			renesas,fcp = <&fcpvi0>;
+		};
+
 		fcpvi0: fcp@fe9af000 {
 			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
 			reg = <0 0xfe9af000 0 0x200>;
@@ -1316,6 +1346,16 @@ 
 			power-domains = <&sysc R8A7795_PD_A3VP>;
 		};
 
+		vspi1: vsp@fe9b0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe9b0000 0 0x8000>;
+			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 630>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+
+			renesas,fcp = <&fcpvi1>;
+		};
+
 		fcpvi1: fcp@fe9bf000 {
 			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
 			reg = <0 0xfe9bf000 0 0x200>;
@@ -1323,6 +1363,16 @@ 
 			power-domains = <&sysc R8A7795_PD_A3VP>;
 		};
 
+		vspi2: vsp@fe9c0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfe9c0000 0 0x8000>;
+			interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 629>;
+			power-domains = <&sysc R8A7795_PD_A3VP>;
+
+			renesas,fcp = <&fcpvi2>;
+		};
+
 		fcpvi2: fcp@fe9cf000 {
 			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
 			reg = <0 0xfe9cf000 0 0x200>;
@@ -1330,6 +1380,16 @@ 
 			power-domains = <&sysc R8A7795_PD_A3VP>;
 		};
 
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x4000>;
+			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 623>;
+			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+
+			renesas,fcp = <&fcpvd0>;
+		};
+
 		fcpvd0: fcp@fea27000 {
 			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
 			reg = <0 0xfea27000 0 0x200>;
@@ -1337,6 +1397,16 @@ 
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 		};
 
+		vspd1: vsp@fea28000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea28000 0 0x4000>;
+			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 622>;
+			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+
+			renesas,fcp = <&fcpvd1>;
+		};
+
 		fcpvd1: fcp@fea2f000 {
 			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
 			reg = <0 0xfea2f000 0 0x200>;
@@ -1344,6 +1414,16 @@ 
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 		};
 
+		vspd2: vsp@fea30000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea30000 0 0x4000>;
+			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 621>;
+			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+
+			renesas,fcp = <&fcpvd2>;
+		};
+
 		fcpvd2: fcp@fea37000 {
 			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
 			reg = <0 0xfea37000 0 0x200>;
@@ -1351,6 +1431,16 @@ 
 			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 		};
 
+		vspd3: vsp@fea38000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea38000 0 0x4000>;
+			interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 620>;
+			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+
+			renesas,fcp = <&fcpvd3>;
+		};
+
 		fcpvd3: fcp@fea3f000 {
 			compatible = "renesas,r8a7795-fcpv", "renesas,fcpv";
 			reg = <0 0xfea3f000 0 0x200>;