From patchwork Mon Aug 22 14:44:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 9293651 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A8A6E607D0 for ; Mon, 22 Aug 2016 14:46:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9C2DA28834 for ; Mon, 22 Aug 2016 14:46:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9106C289AE; Mon, 22 Aug 2016 14:46:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D050428A0B for ; Mon, 22 Aug 2016 14:46:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755243AbcHVOqA (ORCPT ); Mon, 22 Aug 2016 10:46:00 -0400 Received: from newton.telenet-ops.be ([195.130.132.45]:36687 "EHLO newton.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755158AbcHVOp4 (ORCPT ); Mon, 22 Aug 2016 10:45:56 -0400 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by newton.telenet-ops.be (Postfix) with ESMTP id 3sHxFY2y3pzMrX8j for ; Mon, 22 Aug 2016 16:45:37 +0200 (CEST) Received: from ayla.of.borg ([84.193.137.253]) by baptiste.telenet-ops.be with bizsmtp id aEkX1t00x5UCtCs01EkXvd; Mon, 22 Aug 2016 16:44:34 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1bbqSl-0005Z1-QS; Mon, 22 Aug 2016 16:44:31 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1bbqSo-0001Zh-5s; Mon, 22 Aug 2016 16:44:34 +0200 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Hisashi Nakamura , Sergei Shtylyov , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH/RFT 2/4] ARM: shmobile: apmu: Add debug resource reset for secondary CPU boot Date: Mon, 22 Aug 2016 16:44:27 +0200 Message-Id: <1471877069-4157-3-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471877069-4157-1-git-send-email-geert+renesas@glider.be> References: <1471877069-4157-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In debug mode (MD21=1), reset requests derived from power-shutoff to the AP-system CPU cores must be enabled before the AP-system cores first resume from power-shutoff. Else resume may fail, causing the system to hang during boot. As setting these bits is a no-op in normal mode, there's no need to check the actual state of MD21 first. Inspired by CPU-specific patches in the BSP by Hisashi Nakamura . Signed-off-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/platsmp-apmu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 933f9b9024050223..7e4ca6788be521dc 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c @@ -35,12 +35,18 @@ static struct { #define PSTR_OFFS 0x40 /* Power Status Register */ #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n))) /* CPUn Power Status Control Register */ +#define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */ /* Power Status Register */ #define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */ #define CPUST_RUN 0 /* Run Mode */ #define CPUST_STANDBY 3 /* CoreStandby Mode */ +/* Debug Resource Reset Control Register */ +#define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */ +#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */ +#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */ + static int __maybe_unused apmu_power_on(void __iomem *p, int bit) { /* request power on */ @@ -84,6 +90,8 @@ static int __maybe_unused apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu) #ifdef CONFIG_SMP static void apmu_init_cpu(struct resource *res, int cpu, int bit) { + u32 x; + if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem) return; @@ -91,6 +99,11 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit) apmu_cpus[cpu].bit = bit; pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res); + + /* Setup for debug mode */ + x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS); + x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN; + writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS); } static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),