diff mbox

[1/4] clk: shmobile: r8a7796: Add RAVB clock

Message ID 1473150352-31081-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show

Commit Message

Laurent Pinchart Sept. 6, 2016, 8:25 a.m. UTC 
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Geert Uytterhoeven Sept. 6, 2016, 8:59 a.m. UTC | #1 
Hi Laurent,

On Tue, Sep 6, 2016 at 10:25 AM, Laurent Pinchart
<laurent.pinchart+renesas@ideasonboard.com> wrote:
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>  drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> index cfd5ffb77dfe..868dfe30dfe7 100644
> --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> @@ -99,6 +99,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
>  static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
>         DEF_MOD("scif2",                 310,   R8A7796_CLK_S3D4),
>         DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
> +       DEF_MOD("etheravb",              812,   R8A7796_CLK_S3D2),

According to the datasheet, the parent clock on M3-W (and H3 ES2.0!) is S0D6,
not S3D2.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Laurent Pinchart Sept. 6, 2016, 1:53 p.m. UTC | #2 
Hi Geert,

On Tuesday 06 Sep 2016 10:59:47 Geert Uytterhoeven wrote:
> On Tue, Sep 6, 2016 at 10:25 AM, Laurent Pinchart wrote:
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com>
> > ---
> > 
> >  drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> > b/drivers/clk/renesas/r8a7796-cpg-mssr.c index cfd5ffb77dfe..868dfe30dfe7
> > 100644
> > --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
> > @@ -99,6 +99,7 @@ static const struct cpg_core_clk r8a7796_core_clks[]
> > __initconst = {> 
> >  static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
> >         DEF_MOD("scif2",                 310,   R8A7796_CLK_S3D4),
> >         DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
> > +       DEF_MOD("etheravb",              812,   R8A7796_CLK_S3D2),
> 
> According to the datasheet, the parent clock on M3-W (and H3 ES2.0!) is
> S0D6, not S3D2.

Indeed, I'll fix that.

Supporting H3 ES2.0 will be so much fun :-)
diff mbox

Patch

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index cfd5ffb77dfe..868dfe30dfe7 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -99,6 +99,7 @@  static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
 static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
 	DEF_MOD("scif2",		 310,	R8A7796_CLK_S3D4),
 	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S3D1),
+	DEF_MOD("etheravb",		 812,	R8A7796_CLK_S3D2),
 	DEF_MOD("gpio7",		 905,	R8A7796_CLK_S3D4),
 	DEF_MOD("gpio6",		 906,	R8A7796_CLK_S3D4),
 	DEF_MOD("gpio5",		 907,	R8A7796_CLK_S3D4),