| Message ID | 1488909806-3322-4-git-send-email-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | a681e6d63285b879bb9bab0bd79e2021e6dcbda1 |
| Delegated to: | Simon Horman |
| Headers | show |
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 454e1292f9108b34..b951f5ffe9e0faa0 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -61,6 +61,13 @@ cache-unified; cache-level = <2>; }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; }; extal_clk: extal {
Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Extracted from a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: - Drop unit address and reg property for integrated cache-controller. --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)