diff mbox

[09/13] ARM: dts: r8a7792: add [H]SCIF support

Message ID 1493287.pGnW6U6caN@wasted.cogentembedded.com (mailing list archive)
State Superseded
Delegated to: Simon Horman
Headers show

Commit Message

Sergei Shtylyov May 31, 2016, 10:26 p.m. UTC
Describe [H]SCIFs in the R8A7792 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm/boot/dts/r8a7792.dtsi |   90 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

Comments

Simon Horman June 1, 2016, 1:13 a.m. UTC | #1
On Wed, Jun 01, 2016 at 01:26:56AM +0300, Sergei Shtylyov wrote:
> Describe [H]SCIFs in the R8A7792 device tree.
> 
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

This looks correct to me.

I am wondering if you have been able to confirm DMA operation of the
devices enabled later on in the series.

> 
> ---
>  arch/arm/boot/dts/r8a7792.dtsi |   90 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 90 insertions(+)
> 
> Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
> ===================================================================
> --- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
> +++ renesas/arch/arm/boot/dts/r8a7792.dtsi
> @@ -140,6 +140,96 @@
>  		dma-channels = <15>;
>  	};
>  
> +	scif0: serial@e6e60000 {
> +		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
> +			     "renesas,scif";
> +		reg = <0 0xe6e60000 0 64>;
> +		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
> +		       <&dmac1 0x29>, <&dmac1 0x2a>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	scif1: serial@e6e68000 {
> +		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
> +			     "renesas,scif";
> +		reg = <0 0xe6e68000 0 64>;
> +		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
> +		       <&dmac1 0x2d>, <&dmac1 0x2e>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	scif2: serial@e6e58000 {
> +		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
> +			     "renesas,scif";
> +		reg = <0 0xe6e58000 0 64>;
> +		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
> +		       <&dmac1 0x2b>, <&dmac1 0x2c>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	scif3: serial@e6ea8000 {
> +		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
> +			     "renesas,scif";
> +		reg = <0 0xe6ea8000 0 64>;
> +		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
> +		       <&dmac1 0x2f>, <&dmac1 0x30>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	hscif0: serial@e62c0000 {
> +		compatible = "renesas,hscif-r8a7792", "renesas,rcar-gen2-hscif",
> +			     "renesas,hscif";
> +		reg = <0 0xe62c0000 0 96>;
> +		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
> +		       <&dmac1 0x39>, <&dmac1 0x3a>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
> +	hscif1: serial@e62c8000 {
> +		compatible = "renesas,hscif-r8a7792", "renesas,rcar-gen2-hscif",
> +			     "renesas,hscif";
> +		reg = <0 0xe62c8000 0 96>;
> +		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
> +			 <&scif_clk>;
> +		clock-names = "fck", "brg_int", "scif_clk";
> +		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
> +		       <&dmac1 0x4d>, <&dmac1 0x4e>;
> +		dma-names = "tx", "rx", "tx", "rx";
> +		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
> +		status = "disabled";
> +	};
> +
>  	clocks {
>  		#address-cells = <2>;
>  		#size-cells = <2>;
>
Geert Uytterhoeven June 1, 2016, 8:17 a.m. UTC | #2
On Wed, Jun 1, 2016 at 12:26 AM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe [H]SCIFs in the R8A7792 device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Sergei Shtylyov June 3, 2016, 2:33 p.m. UTC | #3
On 06/01/2016 04:13 AM, Simon Horman wrote:

>> Describe [H]SCIFs in the R8A7792 device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> This looks correct to me.
>
> I am wondering if you have been able to confirm DMA operation of the
> devices enabled later on in the series.

    The SCIF DMA seems to work now that enabled it in the driver. Not sure 
what you meant by "the devices enabled later in the seties"...

MBR, Sergei
diff mbox

Patch

Index: renesas/arch/arm/boot/dts/r8a7792.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi
+++ renesas/arch/arm/boot/dts/r8a7792.dtsi
@@ -140,6 +140,96 @@ 
 		dma-channels = <15>;
 	};
 
+	scif0: serial@e6e60000 {
+		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
+		reg = <0 0xe6e60000 0 64>;
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+		       <&dmac1 0x29>, <&dmac1 0x2a>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	scif1: serial@e6e68000 {
+		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
+		reg = <0 0xe6e68000 0 64>;
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	scif2: serial@e6e58000 {
+		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
+		reg = <0 0xe6e58000 0 64>;
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	scif3: serial@e6ea8000 {
+		compatible = "renesas,scif-r8a7792", "renesas,rcar-gen2-scif",
+			     "renesas,scif";
+		reg = <0 0xe6ea8000 0 64>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+		       <&dmac1 0x2f>, <&dmac1 0x30>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	hscif0: serial@e62c0000 {
+		compatible = "renesas,hscif-r8a7792", "renesas,rcar-gen2-hscif",
+			     "renesas,hscif";
+		reg = <0 0xe62c0000 0 96>;
+		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+		       <&dmac1 0x39>, <&dmac1 0x3a>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
+	hscif1: serial@e62c8000 {
+		compatible = "renesas,hscif-r8a7792", "renesas,rcar-gen2-hscif",
+			     "renesas,hscif";
+		reg = <0 0xe62c8000 0 96>;
+		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
+			 <&scif_clk>;
+		clock-names = "fck", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;