From patchwork Tue Aug 8 10:56:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 9887399 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1CD0C60352 for ; Tue, 8 Aug 2017 11:11:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1031828724 for ; Tue, 8 Aug 2017 11:11:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 051CB2875E; Tue, 8 Aug 2017 11:11:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A58ED28724 for ; Tue, 8 Aug 2017 11:11:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752051AbdHHLLS (ORCPT ); Tue, 8 Aug 2017 07:11:18 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:48310 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751998AbdHHLLR (ORCPT ); Tue, 8 Aug 2017 07:11:17 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie2.idc.renesas.com with ESMTP; 08 Aug 2017 20:11:17 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 25A8F71808; Tue, 8 Aug 2017 20:11:17 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.41,342,1498489200"; d="scan'208";a="252842359" Received: from unknown (HELO be1yocto.ree.adwin.renesas.com) ([172.29.43.62]) by relmlii1.idc.renesas.com with ESMTP; 08 Aug 2017 20:11:14 +0900 From: Biju Das To: Rob Herring , Mark Rutland Cc: Simon Horman , Magnus Damm , Russell King , Chris Paterson , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Biju Das Subject: [PATCH 3/3] ARM: dts: r8a7743: Add OPP table for frequency scaling Date: Tue, 8 Aug 2017 11:56:33 +0100 Message-Id: <1502189793-59679-4-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1502189793-59679-1-git-send-email-biju.das@bp.renesas.com> References: <1502189793-59679-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - clock-latency = 300 us Approximate worst-case latency to do clock transition for every OPPs. Using an arbitrary safe value similar to r8a7791(R-Car M2) Soc. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since DVS is not supported in RZ/G1 Soc. Note:This also fixes the below errors seen on kernel logs [ 0.876877] cpu cpu0: dev_pm_opp_get_opp_count: OPP table not found (-19) [ 0.883727] cpu cpu1: cpufreq_init: failed to get clk: -2 Signed-off-by: Biju Das --- arch/arm/boot/dts/r8a7743.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 77da319..8c46f62 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -29,8 +29,17 @@ reg = <0>; clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7743_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; cpu1: cpu@1 {