| Message ID | 1504106234-41450-1-git-send-email-biju.das@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | d6ee805325b1d082fa33be3024163e5f7931ed54 |
| Delegated to: | Simon Horman |
| Headers | show |
On Wed, Aug 30, 2017 at 04:17:14PM +0100, Biju Das wrote: > Define the iWave RainboW-G22D board dependent part of the Ethernet > AVB device node. > > On some older versions of the platform (before R4.0) the phy address > may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which > will be the first mainstream release), hence using 3 in the dts. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> > --- > This patch is tested against renesas-dev tag 20170830-v4.13-rc7 > > arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts > index 442a5cb..aac84c6 100644 > --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts > +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts > @@ -17,9 +17,11 @@ > > aliases { > serial0 = &scif4; > + ethernet0 = &avb; > }; > > chosen { > + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; > stdout-path = "serial0:115200n8"; > }; > }; > @@ -29,6 +31,11 @@ > groups = "scif4_data_b"; > function = "scif4"; > }; > + > + avb_pins: avb { > + groups = "avb_mdio", "avb_gmii"; > + function = "avb"; > + }; > }; > > &scif4 { > @@ -37,3 +44,22 @@ > > status = "okay"; > }; > + > +&avb { > + pinctrl-0 = <&avb_pins>; > + pinctrl-names = "default"; > + > + phy-handle = <&phy3>; > + phy-mode = "gmii"; > + renesas,no-ether-link; > + status = "okay"; > + > + phy3: ethernet-phy@3 { > + /* > + * On some older versions of the platform (before R4.0) the phy address > + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. > + */ > + reg = <3>; > + micrel,led-mode = <1>; Does the phy have an interrupt? > + }; > +}; > -- > 1.9.1 >
> -----Original Message----- > From: Simon Horman [mailto:horms@verge.net.au] > Sent: 31 August 2017 09:46 > To: Biju Das <biju.das@bp.renesas.com> > Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland > <mark.rutland@arm.com>; Magnus Damm <magnus.damm@gmail.com>; > Russell King <linux@armlinux.org.uk>; Chris Paterson > <Chris.Paterson2@renesas.com>; devicetree@vger.kernel.org; linux-renesas- > soc@vger.kernel.org; linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH ] ARM: dts: iwg22d-sodimm: Add Ethernet AVB support > > On Wed, Aug 30, 2017 at 04:17:14PM +0100, Biju Das wrote: > > Define the iWave RainboW-G22D board dependent part of the Ethernet AVB > > device node. > > > > On some older versions of the platform (before R4.0) the phy address > > may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which will > > be the first mainstream release), hence using 3 in the dts. > > > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> > > Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> > > --- > > This patch is tested against renesas-dev tag 20170830-v4.13-rc7 > > > > arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 26 > > ++++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts > > b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts > > index 442a5cb..aac84c6 100644 > > --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts > > +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts > > @@ -17,9 +17,11 @@ > > > > aliases { > > serial0 = &scif4; > > +ethernet0 = &avb; > > }; > > > > chosen { > > +bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; > > stdout-path = "serial0:115200n8"; > > }; > > }; > > @@ -29,6 +31,11 @@ > > groups = "scif4_data_b"; > > function = "scif4"; > > }; > > + > > +avb_pins: avb { > > +groups = "avb_mdio", "avb_gmii"; > > +function = "avb"; > > +}; > > }; > > > > &scif4 { > > @@ -37,3 +44,22 @@ > > > > status = "okay"; > > }; > > + > > +&avb { > > +pinctrl-0 = <&avb_pins>; > > +pinctrl-names = "default"; > > + > > +phy-handle = <&phy3>; > > +phy-mode = "gmii"; > > +renesas,no-ether-link; > > +status = "okay"; > > + > > +phy3: ethernet-phy@3 { > > +/* > > + * On some older versions of the platform (before R4.0) the phy > address > > + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. > > + */ > > +reg = <3>; > > +micrel,led-mode = <1>; > > Does the phy have an interrupt? The current board doesn't support interrupt . But there is a plan to support this in future board variants through (GPIO3_28). > > +}; > > +}; > > -- > > 1.9.1 > > Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
Hello, > From: Biju Das > Sent: 31 August 2017 10:24 > > > From: Simon Horman [mailto:horms@verge.net.au] > > Sent: 31 August 2017 09:46 <snip> > > > + phy3: ethernet-phy@3 { > > > + /* > > > + * On some older versions of the platform (before R4.0) the phy > > address > > > + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. > > > + */ > > > + reg = <3>; > > > + micrel,led-mode = <1>; > > > > Does the phy have an interrupt? > > The current board doesn't support interrupt . But there is a plan to support this > in future board variants through (GPIO3_28). Actually, the plan has recently changed and at the moment interrupt support will not be added in the production version of the board. If in the end the plan changes again and the actual hardware does add interrupt support we'll submit a new patch accordingly. Kind regards, Chris
On Thu, Aug 31, 2017 at 09:32:25AM +0000, Chris Paterson wrote: > Hello, > > > From: Biju Das > > Sent: 31 August 2017 10:24 > > > > > From: Simon Horman [mailto:horms@verge.net.au] > > > Sent: 31 August 2017 09:46 > > <snip> > > > > > + phy3: ethernet-phy@3 { > > > > + /* > > > > + * On some older versions of the platform (before R4.0) the phy > > > address > > > > + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. > > > > + */ > > > > + reg = <3>; > > > > + micrel,led-mode = <1>; > > > > > > Does the phy have an interrupt? > > > > The current board doesn't support interrupt . But there is a plan to support this > > in future board variants through (GPIO3_28). > > Actually, the plan has recently changed and at the moment interrupt support will not be added in the production version of the board. > > If in the end the plan changes again and the actual hardware does add interrupt support we'll submit a new patch accordingly. Thanks for following-up on this. I'm still surprised there is no interrupt - does link speed renegotiation initiated by the other end of the link work in a timely manner? - but if its not there and my wishful thinking won't make it so. I have applied this patch for v4.15.
Hi Simon, On Fri, Sep 1, 2017 at 10:49 AM, Simon Horman <horms@verge.net.au> wrote: > On Thu, Aug 31, 2017 at 09:32:25AM +0000, Chris Paterson wrote: >> > From: Biju Das >> > > From: Simon Horman [mailto:horms@verge.net.au] >> > > > + phy3: ethernet-phy@3 { >> > > > + /* >> > > > + * On some older versions of the platform (before R4.0) the phy >> > > address >> > > > + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. >> > > > + */ >> > > > + reg = <3>; >> > > > + micrel,led-mode = <1>; >> > > >> > > Does the phy have an interrupt? >> > >> > The current board doesn't support interrupt . But there is a plan to support this >> > in future board variants through (GPIO3_28). >> >> Actually, the plan has recently changed and at the moment interrupt support will not be added in the production version of the board. >> >> If in the end the plan changes again and the actual hardware does add interrupt support we'll submit a new patch accordingly. > > Thanks for following-up on this. I'm still surprised there is no interrupt > - does link speed renegotiation initiated by the other end of the link work > in a timely manner? - but if its not there and my wishful thinking won't > make it so. I guess it behaves similar to Koelsch using the new CPG/MSSR driver, and without the probe deferral fix for of_mdio, where it also falls back to polling. Cfr. the figures in https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg17422.html Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index 442a5cb..aac84c6 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -17,9 +17,11 @@ aliases { serial0 = &scif4; + ethernet0 = &avb; }; chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; }; @@ -29,6 +31,11 @@ groups = "scif4_data_b"; function = "scif4"; }; + + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; }; &scif4 { @@ -37,3 +44,22 @@ status = "okay"; }; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + /* + * On some older versions of the platform (before R4.0) the phy address + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. + */ + reg = <3>; + micrel,led-mode = <1>; + }; +};