From patchwork Tue Sep 12 08:40:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 9948635 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 33F1860360 for ; Tue, 12 Sep 2017 08:42:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2509F2839C for ; Tue, 12 Sep 2017 08:42:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 19EAE2852C; Tue, 12 Sep 2017 08:42:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A89062851B for ; Tue, 12 Sep 2017 08:42:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751332AbdILImA (ORCPT ); Tue, 12 Sep 2017 04:42:00 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:51536 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751337AbdILIlD (ORCPT ); Tue, 12 Sep 2017 04:41:03 -0400 Received: from ayla.of.borg ([84.195.106.246]) by xavier.telenet-ops.be with bizsmtp id 8Ygz1w00g5JzmfG01YgzyB; Tue, 12 Sep 2017 10:41:02 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1drgkZ-0003Xv-DR; Tue, 12 Sep 2017 10:40:55 +0200 Received: from geert by ramsan with local (Exim 4.86_2) (envelope-from ) id 1drgkd-0004hJ-Ln; Tue, 12 Sep 2017 10:40:59 +0200 From: Geert Uytterhoeven To: Andrew Morton Cc: Yoshinori Sato , Rich Felker , Magnus Damm , Laurent Pinchart , Yoshihiro Shimoda , linux-sh@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 resend 1/4] sh: sh7722: Remove nonexistent GPIO_PTQ7 to fix pinctrl registration Date: Tue, 12 Sep 2017 10:40:54 +0200 Message-Id: <1505205657-18012-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505205657-18012-1-git-send-email-geert+renesas@glider.be> References: <1505205657-18012-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On sh7722/Migo-R, pinctrl registration fails with: sh-pfc pfc-sh7722: pin 0 already registered sh-pfc pfc-sh7722: error during pin registration sh-pfc pfc-sh7722: could not register: -22 sh-pfc: probe of pfc-sh7722 failed with error -22 pinmux_pins[] is initialized through PINMUX_GPIO(), using designated array initializers, where the GPIO_* enums serve as indices. As GPIO_PTQ7 is defined in the enum, but never used, pinmux_pins[] contains a (zero-filled) hole. Hence this entry is treated as pin zero, which was registered before, and pinctrl registration fails. According to the datasheet, port PTQ7 does not exist. Hence remove GPIO_PTQ7 from the enum to fix this. Fixes: 8d7b5b0af7e070b9 ("sh: Add sh7722 pinmux code") Reported-by: Magnus Damm Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Tested-by: Jacopo Mondi --- Tested on sh7722/Migo-R. v2: - Add Reviewed-by, Tested-by. --- arch/sh/include/cpu-sh4/cpu/sh7722.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h index 3bb74e534d0f8ca4..78961ab78a5a9c83 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7722.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h @@ -67,7 +67,7 @@ enum { GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0, /* PTQ */ - GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4, + GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4, GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0, /* PTR */