From patchwork Wed Sep 13 17:05:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Paterson X-Patchwork-Id: 9951703 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 31589604D5 for ; Wed, 13 Sep 2017 17:06:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1DE4E289EB for ; Wed, 13 Sep 2017 17:06:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 12D1228822; Wed, 13 Sep 2017 17:06:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE35E28AB0 for ; Wed, 13 Sep 2017 17:06:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751348AbdIMRGT (ORCPT ); Wed, 13 Sep 2017 13:06:19 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:16636 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751167AbdIMRGS (ORCPT ); Wed, 13 Sep 2017 13:06:18 -0400 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie2.idc.renesas.com with ESMTP; 14 Sep 2017 02:06:17 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id D019D4C007; Thu, 14 Sep 2017 02:06:17 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.42,389,1500908400"; d="scan'208";a="257789620" Received: from unknown (HELO renesas-VirtualBox.ree.adwin.renesas.com) ([10.226.36.243]) by relmlii2.idc.renesas.com with ESMTP; 14 Sep 2017 02:06:13 +0900 From: Chris Paterson To: Simon Horman Cc: Rob Herring , Mark Rutland , Magnus Damm , Russell King , Fabrizio Castro , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Paterson Subject: [PATCH 8/8] ARM: drs: iwg22m: Add SPI NOR support Date: Wed, 13 Sep 2017 18:05:41 +0100 Message-Id: <1505322341-9480-9-git-send-email-chris.paterson2@renesas.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505322341-9480-1-git-send-email-chris.paterson2@renesas.com> References: <1505322341-9480-1-git-send-email-chris.paterson2@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Fabrizio Castro Add support for the SPI NOR device used to boot up the system to the System on Module DT. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven --- This patch is based on renesas-devel-20170913-v4.13. This patch is dependant on: - "of: add vendor prefix for Silicon Storage Technology Inc." - "doc: dt: mtd: Add sst25vf016b to the list of supported chip names" arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi index f7f9cef..ed9a8cf 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -39,6 +39,11 @@ function = "mmc"; }; + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + sdhi1_pins: sd1 { groups = "sdhi1_data4", "sdhi1_ctrl"; function = "sdhi1"; @@ -61,6 +66,27 @@ status = "okay"; }; +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-names = "default";