From patchwork Thu Oct 5 13:26:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 9987179 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 26E1860291 for ; Thu, 5 Oct 2017 13:27:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 107A428C84 for ; Thu, 5 Oct 2017 13:27:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0F17C28C92; Thu, 5 Oct 2017 13:27:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1398B28CC5 for ; Thu, 5 Oct 2017 13:27:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751409AbdJEN1H (ORCPT ); Thu, 5 Oct 2017 09:27:07 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:37175 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751310AbdJEN1G (ORCPT ); Thu, 5 Oct 2017 09:27:06 -0400 Received: from penelope.horms.nl (unknown [217.111.208.18]) by kirsty.vergenet.net (Postfix) with ESMTPA id 1C61525B7AB; Fri, 6 Oct 2017 00:27:04 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1507210025; bh=XpEAbNFkeezq7S0Xi43FbsyPcroSBO16Pf2pGDszhzI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B64Wq5BRx6mf4wOA3tr0VxgoroDgAJn2Cf5AJ5EEgdCmsHCLcw+cdpQdqhCyd9qkc VtinEl4sKEr4fHWuytFaSq+5SO3ANsxLZqdZ2PFPI7gZZbEPMbm4izwW0VukaLiIrk xRFqnhBltVO9be7jcW/QbkjiUKCj8yGI6tND0cSc= Received: by penelope.horms.nl (Postfix, from userid 7100) id 22E94E20AAE; Thu, 5 Oct 2017 09:26:27 -0400 (EDT) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm Subject: [PATCH v2 1/2] arm64: dts: r8a7795: Add OPPs table for cpu devices Date: Thu, 5 Oct 2017 15:26:23 +0200 Message-Id: <1507209984-17123-2-git-send-email-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1507209984-17123-1-git-send-email-horms+renesas@verge.net.au> References: <1507209984-17123-1-git-send-email-horms+renesas@verge.net.au> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dien Pham Current, OPP tables are defined temporary, they are being evaluated and adjust in future. Based in part on work by Hien Dang. Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman --- v2 [Simon Horman] - Only provide one operating points node for each operating-points-v2 node as per the binding; other nodes were unused and have been removed v1 [Simon Horman] - consolidated several patches into one v0 [Dien Pham] --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 55 ++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index d5cfd1a1c539..9cf63a1f0c35 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -46,6 +46,8 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a57_1: cpu@1 { @@ -55,6 +57,7 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; a57_2: cpu@2 { @@ -64,6 +67,7 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; a57_3: cpu@3 { @@ -73,6 +77,7 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; a53_0: cpu@100 { @@ -82,6 +87,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; }; a53_1: cpu@101 { @@ -91,6 +98,7 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; }; a53_2: cpu@102 { @@ -100,6 +108,7 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; }; a53_3: cpu@103 { @@ -109,6 +118,7 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; }; L2_CA57: cache-controller-0 { @@ -126,6 +136,51 @@ }; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp@1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp@1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp@1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>;