diff mbox

[v2,12/18] arm64: dts: ulcb-kf: enable PCIE0/1

Message ID 1507257839-12066-1-git-send-email-vladimir.barinov@cogentembedded.com (mailing list archive)
State Accepted
Commit e0304a365bf07b4a0bb2d56ece5b52f3347d5a01
Delegated to: Simon Horman
Headers show

Commit Message

Vladimir Barinov Oct. 6, 2017, 2:43 a.m. UTC 
This supports PCIE0/1 on ULCB Kingfisher board

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- removed status update for pcie_bus_clk

 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Simon Horman Oct. 9, 2017, 7:16 a.m. UTC | #1 
On Fri, Oct 06, 2017 at 05:43:59AM +0300, Vladimir Barinov wrote:
> This supports PCIE0/1 on ULCB Kingfisher board
> 
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, applied.
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 46e3a34..952d2b7 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -52,6 +52,18 @@ 
 	status = "okay";
 };
 
+&pcie_bus_clk {
+	clock-frequency = <100000000>;
+};
+
+&pciec0 {
+	status = "okay";
+};
+
+&pciec1 {
+	status = "okay";
+};
+
 &pfc {
 	can0_pins: can0 {
 		groups = "can0_data_a";