| Message ID | 1507800916-11509-8-git-send-email-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
On Thu, Oct 12, 2017 at 11:35:10AM +0200, Geert Uytterhoeven wrote: > Currently only the primary CPU in the CA15 cluster has a clocks > property, while the secondary CPU cores are driven by the same clock. > Add the missing clocks properties to fix this. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index ffa57bfe4873415c..7f86cb9f634fbed7 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -71,6 +71,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; @@ -80,6 +81,7 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; }; @@ -89,6 +91,7 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; };
Currently only the primary CPU in the CA15 cluster has a clocks property, while the secondary CPU cores are driven by the same clock. Add the missing clocks properties to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- arch/arm/boot/dts/r8a7790.dtsi | 3 +++ 1 file changed, 3 insertions(+)