| Message ID | 1509379633-25823-2-git-send-email-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 75d09f1724f02c1d..583ebb4c5eac0bfe 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -37,6 +37,16 @@ enable-method = "psci"; }; + a53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <1>; + clocks = <&cpg CPG_CORE 0>; + power-domains = <&sysc 6>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller { compatible = "cache"; power-domains = <&sysc 21>;
Add a device node for the second Cortex-A53 CPU core on the Renesas R-Car V3M (r8a77970) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)