From patchwork Wed Dec 6 12:05:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 10095731 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0166D60210 for ; Wed, 6 Dec 2017 12:05:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E71F629C7E for ; Wed, 6 Dec 2017 12:05:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DAFF829CE0; Wed, 6 Dec 2017 12:05:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5FEC829C7E for ; Wed, 6 Dec 2017 12:05:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751066AbdLFMFu (ORCPT ); Wed, 6 Dec 2017 07:05:50 -0500 Received: from relmlor2.renesas.com ([210.160.252.172]:34819 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750812AbdLFMFt (ORCPT ); Wed, 6 Dec 2017 07:05:49 -0500 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie1.idc.renesas.com with ESMTP; 06 Dec 2017 21:05:47 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id EFB258CAB0; Wed, 6 Dec 2017 21:05:47 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.45,367,1508770800"; d="scan'208";a="264334553" Received: from unknown (HELO fabrizio-dev.ree.adwin.renesas.com) ([10.226.36.198]) by relmlii1.idc.renesas.com with ESMTP; 06 Dec 2017 21:05:45 +0900 From: Fabrizio Castro To: Simon Horman Cc: Fabrizio Castro , Rob Herring , Mark Rutland , Magnus Damm , Russell King , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Paterson , Geert Uytterhoeven Subject: [PATCH v2] ARM: dts: r8a7745: Add APMU node and second CPU core Date: Wed, 6 Dec 2017 12:05:29 +0000 Message-Id: <1512561929-16540-1-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method". Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven --- Dear All, I am reposting this patch now that its dependecy ("ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15") is part of v4.15-rc1, similarly to patch "ARM: dts: r8a7794: Add SMP support". v2: - rebased against renesas-devel-20171205-v4.15-rc2 Thanks arch/arm/boot/dts/r8a7745.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index de13e15..0fa7861 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -38,6 +38,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -49,6 +50,15 @@ next-level-cache = <&L2_CA7>; }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clock-frequency = <1000000000>; + power-domains = <&sysc R8A7745_PD_CA7_CPU1>; + next-level-cache = <&L2_CA7>; + }; + L2_CA7: cache-controller-0 { compatible = "cache"; cache-unified; @@ -65,6 +75,12 @@ #size-cells = <2>; ranges; + apmu@e6151000 { + compatible = "renesas,r8a7745-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;