From patchwork Fri Dec 15 15:14:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 10115329 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7400960231 for ; Fri, 15 Dec 2017 15:15:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61EDB29EB8 for ; Fri, 15 Dec 2017 15:15:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 56B1529F0A; Fri, 15 Dec 2017 15:15:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE00829EB8 for ; Fri, 15 Dec 2017 15:15:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756697AbdLOPPA (ORCPT ); Fri, 15 Dec 2017 10:15:00 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:43881 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756600AbdLOPO7 (ORCPT ); Fri, 15 Dec 2017 10:14:59 -0500 Received: by mail-wm0-f65.google.com with SMTP id n138so18089383wmg.2 for ; Fri, 15 Dec 2017 07:14:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=rg+Q6JtW7c7Tz+sLCFqErigPapR+CwfS3r1plDExqkw=; b=rX93eexp102yCLf9FBP8JzfLvTFhbaRvHAuUrnOmAPaM4+s7XuWeYJEoMsdyT0N02K FjMQFHN+R5CobM27/+CKe3+RJ2zjnmhNVUB4AxTnKChdn1GPud4ipjUxLu0Jgpl/YkZb 3lqERzv92/ACMdWlOyTclF+JLpT5qnaXK2alAZYctnWfq1BGaMlZ9V4EkU09ztT3I9QS kubbNWo3bjcxDPRoXD360seKeXdS/5czTVuiqre7pJeN+uDsulXwdJp+FolZaJQVkVya DM2pawxAC1D8HbYE+yvyCith5IfHqVEnT9mOsPAQitBkpXDgck69pq/0IDLdX3++S7E1 mJFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=rg+Q6JtW7c7Tz+sLCFqErigPapR+CwfS3r1plDExqkw=; b=nubaaxClfEkpkqgxsL9Jk3ZT6RIantPuu0d5i/74Ua0ivwyT5z4BIKPBc1vUwhsnLf 2ZzbH6c9fVY1nwEFPDKFE/ngBFyjqkAbCNmAHL+MWTa9tH27BRo8Op+oxKaOHKNWI8vA jltHbZojp9sWc76mYdH4XW8q/kBIT3o9ds0EktMBR5Ah+HiHzXI9Nchpre8AjKb0Uj3v NBW2a2/FqWWU1ef2nMfpMiBDJzthLaJK60DBzxP2DIo/rRBCirxRRknakuCK767QRK7V oFVTsu4kOwdSvKLQmkNa6qqXrIP62z/NUdr14/XgWt7lxQIfDsLzRysIrwmXmcfRtOjo hoBQ== X-Gm-Message-State: AKGB3mKp8ruXkR1XL6R3C/O7zVjZ2VR+WFkPWjx1/Rsj4vH58HiDSj4H e9LZbn5I4764vVsFcxl+HFfpfEE= X-Google-Smtp-Source: ACJfBovabPmJALT2B19G/mE6e1c3NO2NfJMLRENgCY6yFUy/DQWUI+5dL/g2ctV9WP25GFRmFc0BUw== X-Received: by 10.28.16.144 with SMTP id 138mr5189949wmq.155.1513350897800; Fri, 15 Dec 2017 07:14:57 -0800 (PST) Received: from groucho.site (ipbcc3b865.dynamic.kabel-deutschland.de. [188.195.184.101]) by smtp.gmail.com with ESMTPSA id 56sm8406567wrx.73.2017.12.15.07.14.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 15 Dec 2017 07:14:57 -0800 (PST) From: Ulrich Hecht To: linux-renesas-soc@vger.kernel.org Cc: laurent.pinchart@ideasonboard.com, magnus.damm@gmail.com, geert@linux-m68k.org, Takeshi Kihara Subject: [PATCH 2/4] clk: renesas: rcar-gen3: Add ZG clock divider support Date: Fri, 15 Dec 2017 16:14:48 +0100 Message-Id: <1513350890-2446-3-git-send-email-ulrich.hecht+renesas@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513350890-2446-1-git-send-email-ulrich.hecht+renesas@gmail.com> References: <1513350890-2446-1-git-send-email-ulrich.hecht+renesas@gmail.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara This patch adds ZG clock divider support for R-Car Gen3 SoC. Signed-off-by: Takeshi Kihara --- drivers/clk/renesas/rcar-gen3-cpg.c | 120 ++++++++++++++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 1 + 2 files changed, 121 insertions(+) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 102cfc2..6b5d5ec 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -73,6 +73,8 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, */ #define CPG_FRQCRB 0x00000004 #define CPG_FRQCRB_KICK BIT(31) +#define CPG_FRQCRB_ZGFC_MASK (0x1f << 24) +#define CPG_FRQCRB_ZGFC_SHIFT 24 #define CPG_FRQCRC 0x000000e0 #define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8) #define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0) @@ -197,6 +199,120 @@ static struct clk * __init cpg_z_clk_register(const char *name, return clk; } +static unsigned long cpg_zg_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cpg_z_clk *zclk = to_z_clk(hw); + unsigned long prate = parent_rate / 2; /* PLL4 clock divided by 2 */ + unsigned int mult; + unsigned int val; + unsigned long rate; + + val = (clk_readl(zclk->reg) & CPG_FRQCRB_ZGFC_MASK) + >> CPG_FRQCRB_ZGFC_SHIFT; + mult = 32 - val; + + rate = div_u64((u64)prate * mult + 16, 32); + /* Round to closest value at 10MHz unit */ + rate = 10000000 * DIV_ROUND_CLOSEST(rate, 10000000); + + return rate; +} + +static long cpg_zg_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned long prate = *parent_rate / 2; /* PLL4 clock divided by 2 */ + unsigned int mult; + + mult = div_u64((u64)rate * 32 + prate / 2, prate); + mult = clamp(mult, 1U, 32U); + + return prate / 32 * mult; +} + +static int cpg_zg_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct cpg_z_clk *zclk = to_z_clk(hw); + unsigned long prate = parent_rate / 2; /* PLL4 clock divided by 2 */ + unsigned int mult; + u32 val, kick; + unsigned int i; + + mult = div_u64((u64)rate * 32 + prate / 2, prate); + mult = clamp(mult, 1U, 32U); + + if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK) + return -EBUSY; + + val = clk_readl(zclk->reg); + val &= ~CPG_FRQCRB_ZGFC_MASK; + val |= (32 - mult) << CPG_FRQCRB_ZGFC_SHIFT; + clk_writel(val, zclk->reg); + + /* + * Set KICK bit in FRQCRB to update hardware setting and wait for + * clock change completion. + */ + kick = clk_readl(zclk->kick_reg); + kick |= CPG_FRQCRB_KICK; + clk_writel(kick, zclk->kick_reg); + + /* + * Note: There is no HW information about the worst case latency. + * + * Using experimental measurements, it seems that no more than + * ~10 iterations are needed, independently of the CPU rate. + * Since this value might be dependent of external xtal rate, pll1 + * rate or even the other emulation clocks rate, use 1000 as a + * "super" safe value. + */ + for (i = 1000; i; i--) { + if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) + return 0; + + cpu_relax(); + } + + return -ETIMEDOUT; +} + +static const struct clk_ops cpg_zg_clk_ops = { + .recalc_rate = cpg_zg_clk_recalc_rate, + .round_rate = cpg_zg_clk_round_rate, + .set_rate = cpg_zg_clk_set_rate, +}; + +static struct clk * __init cpg_zg_clk_register(const char *name, + const char *parent_name, + void __iomem *reg) +{ + struct clk_init_data init; + struct cpg_z_clk *zclk; + struct clk *clk; + + zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); + if (!zclk) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &cpg_zg_clk_ops; + init.flags = 0; + init.parent_names = &parent_name; + init.num_parents = 1; + + zclk->reg = reg + CPG_FRQCRB; + zclk->kick_reg = reg + CPG_FRQCRB; + zclk->hw.init = &init; + + clk = clk_register(NULL, &zclk->hw); + if (IS_ERR(clk)) + kfree(zclk); + + return clk; +} + /* * SDn Clock */ @@ -564,6 +680,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, return cpg_z_clk_register(core->name, __clk_get_name(parent), base, CPG_FRQCRC_Z2FC_MASK); + case CLK_TYPE_GEN3_ZG: + return cpg_zg_clk_register(core->name, __clk_get_name(parent), + base); + default: return ERR_PTR(-EINVAL); } diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index ea4f8fc..3ae9fe6d 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -23,6 +23,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_PE, CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_Z2, + CLK_TYPE_GEN3_ZG, }; #define DEF_GEN3_SD(_name, _id, _parent, _offset) \