From patchwork Tue Dec 19 16:02:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10123629 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8470F6019C for ; Tue, 19 Dec 2017 16:02:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6E2EE292F8 for ; Tue, 19 Dec 2017 16:02:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 633502930E; Tue, 19 Dec 2017 16:02:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0DAC4292F8 for ; Tue, 19 Dec 2017 16:02:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751136AbdLSQCV (ORCPT ); Tue, 19 Dec 2017 11:02:21 -0500 Received: from andre.telenet-ops.be ([195.130.132.53]:46176 "EHLO andre.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752719AbdLSQCL (ORCPT ); Tue, 19 Dec 2017 11:02:11 -0500 Received: from ayla.of.borg ([84.195.106.246]) by andre.telenet-ops.be with bizsmtp id ns2A1w00D5JzmfG01s2AQ4; Tue, 19 Dec 2017 17:02:10 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1eRKLK-00077q-1d; Tue, 19 Dec 2017 17:02:10 +0100 Received: from geert by ramsan with local (Exim 4.86_2) (envelope-from ) id 1eRKLK-000784-0b; Tue, 19 Dec 2017 17:02:10 +0100 From: Geert Uytterhoeven To: Thierry Reding , Rob Herring , Mark Rutland , Simon Horman , Magnus Damm Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 1/3] ARM: dts: r8a7740: Correct TPU register block size Date: Tue, 19 Dec 2017 17:02:05 +0100 Message-Id: <1513699327-27357-2-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513699327-27357-1-git-send-email-geert+renesas@glider.be> References: <1513699327-27357-1-git-send-email-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Timer Pulse Unit has registers that lie outside the declared register block. Enlarge the register block size to fix this. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- This was probably based on the old platform code, which also assumed a register block size of 0x100. arch/arm/boot/dts/r8a7740.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 95c408b11991fb77..afd3bc5e6cf2e23f 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -317,7 +317,7 @@ tpu: pwm@e6600000 { compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x100>; + reg = <0xe6600000 0x148>; clocks = <&mstp3_clks R8A7740_CLK_TPU0>; power-domains = <&pd_a3sp>; status = "disabled";