| Message ID | 1518602108-1724-4-git-send-email-kbingham@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | d9366032b63bb544fd7d2fd290a922e8484a52c5 |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Kieran, Thank you for the patch. On Wednesday, 14 February 2018 11:55:06 EET Kieran Bingham wrote: > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > The VSPD includes a CLUT on RPF2. Ensure that the register space is > mapped correctly to support this. > > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi > b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index > ed553338b4d4..1adfe6cad268 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi > @@ -80,7 +80,7 @@ > > vspd3: vsp@fea38000 { > compatible = "renesas,vsp2"; > - reg = <0 0xfea38000 0 0x4000>; > + reg = <0 0xfea38000 0 0x8000>; > interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&cpg CPG_MOD 620>; > power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
On Wed, Feb 14, 2018 at 12:08:56PM +0200, Laurent Pinchart wrote: > Hi Kieran, > > Thank you for the patch. > > On Wednesday, 14 February 2018 11:55:06 EET Kieran Bingham wrote: > > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > > > The VSPD includes a CLUT on RPF2. Ensure that the register space is > > mapped correctly to support this. > > > > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Thanks, applied.
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi index ed553338b4d4..1adfe6cad268 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi @@ -80,7 +80,7 @@ vspd3: vsp@fea38000 { compatible = "renesas,vsp2"; - reg = <0 0xfea38000 0 0x4000>; + reg = <0 0xfea38000 0 0x8000>; interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 620>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;