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a=rsa-sha256; c=relaxed/relaxed; d=renesasgroup.onmicrosoft.com; s=selector1-renesas-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=/nho8GCBkVK7AWj3iHz+1O2Ap818kJnUPq9OM+nWpis=; b=pRihH3o8tPpL1A0sPpAKBC7BVsMxOgKZjhqFqGM0dVRwPUkMxNGJdnJ+Ww1H4ZNsSDZreAYFJfPhgF02/BN4BSOZxqSD0MrIhn45adbOxWxUQqcYi4uJ8p7q+WdQ0dNU9pKpABGyQvWw/lL4/hm8N3BrwBsknzT4p0iDH2i0MWo= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=<>; Received: from localhost.localdomain (211.11.155.138) by HK2PR06MB0978.apcprd06.prod.outlook.com (2a01:111:e400:589d::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.696.13; Fri, 20 Apr 2018 12:28:35 +0000 From: Yoshihiro Shimoda To: horms@verge.net.au, magnus.damm@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Takeshi Kihara , Yoshihiro Shimoda Subject: [PATCH v2 2/2] arm64: dts: renesas: Add Renesas Ebisu board support Date: Fri, 20 Apr 2018 21:28:17 +0900 Message-Id: <1524227297-24955-3-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1524227297-24955-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> References: <1524227297-24955-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Originating-IP: [211.11.155.138] X-ClientProxiedBy: TYAPR01CA0139.jpnprd01.prod.outlook.com (2603:1096:404:2d::31) To HK2PR06MB0978.apcprd06.prod.outlook.com (2a01:111:e400:589d::24) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; 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20:0lt8XC4ISgODxUrhpT5d9V4OphlfMUowosUzUztx5MNlxQWYJlCXjqj+ngmtgsB0Q182vkBCA45yv2nD+2hSMoV0qDCTs89vvBvKv1Q419uHHklhiAmMSQiz6j+9VLX8yUVuzwjg//fr5T+hPNMZaB3Hm4Mbg+T9cLRbxIdlf/s= X-MS-Office365-Filtering-Correlation-Id: 0c734442-aee6-4e6d-f37e-08d5a6ba3d0b X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2018 12:28:35.5176 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c734442-aee6-4e6d-f37e-08d5a6ba3d0b X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK2PR06MB0978 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Basic support for the Renesas Ebisu board based on R-Car E3: - Memory, - Main crystal, - Serial console, Signed-off-by: Takeshi Kihara [shimoda: rebase and add SPDX-License-Identifier] Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 37 ++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 5ede060..a235961 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -10,4 +10,5 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb +dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts new file mode 100644 index 0000000..63ee134 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree Source for the ebisu board + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77990.dtsi" + +/ { + model = "Renesas Ebisu board based on r8a77990"; + compatible = "renesas,ebisu", "renesas,r8a77990"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&scif2 { + status = "okay"; +};