From patchwork Tue Jun 5 08:29:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Pollet X-Patchwork-Id: 10447847 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B150660375 for ; Tue, 5 Jun 2018 08:36:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A3B2F28EB0 for ; Tue, 5 Jun 2018 08:36:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 966E828EE3; Tue, 5 Jun 2018 08:36:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5612728EB0 for ; Tue, 5 Jun 2018 08:36:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751765AbeFEIgO (ORCPT ); Tue, 5 Jun 2018 04:36:14 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:43289 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751662AbeFEIgM (ORCPT ); Tue, 5 Jun 2018 04:36:12 -0400 Received: from unknown (HELO relmlir2.idc.renesas.com) ([10.200.68.152]) by relmlie3.idc.renesas.com with ESMTP; 05 Jun 2018 17:36:10 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir2.idc.renesas.com (Postfix) with ESMTP id 524867B71B; Tue, 5 Jun 2018 17:36:10 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.49,478,1520866800"; d="scan'208";a="283073147" Received: from unknown (HELO be1yocto.ree.adwin.renesas.com) ([172.29.43.62]) by relmlii2.idc.renesas.com with ESMTP; 05 Jun 2018 17:36:05 +0900 From: Michel Pollet To: linux-renesas-soc@vger.kernel.org, Simon Horman Cc: phil.edworthy@renesas.com, Michel Pollet , Michel Pollet , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Geert Uytterhoeven , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 2/5] dt-bindings: clock: renesas, r9a06g032-sysctrl: documentation Date: Tue, 5 Jun 2018 09:29:58 +0100 Message-Id: <1528187462-47093-3-git-send-email-michel.pollet@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528187462-47093-1-git-send-email-michel.pollet@bp.renesas.com> References: <1528187462-47093-1-git-send-email-michel.pollet@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Renesas R9A06G032 SYSCTRL node description. Signed-off-by: Michel Pollet --- .../bindings/clock/renesas,r9a06g032-sysctrl.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt new file mode 100644 index 0000000..6aee360 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt @@ -0,0 +1,32 @@ +* Renesas R9A06G032 SYSCTRL + +Required Properties: + + - compatible: Must be: + - "renesas,r9a06g032-sysctrl" + - reg: Base address and length of the SYSCTRL IO block. + - #clock-cells: Must be 1 + +Examples +-------- + + - SYSCTRL node: + + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + #clock-cells = <1>; + }; + + - Other nodes can use the clocks provided by SYSCTRL as in: + + #include + uart0: serial@40060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART0>; + clock-names = "baudclk"; + };